Patent EP0389697A2 successfully refreshed from Google Patents.
EP0389697A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Serial data receiver
Assignee: International Business Machines Corp
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Filing: 1989-03-29
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Granted: —
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Expires: 2009-03-29
Abstract
Abstract An asynchronous serial data receiver for receiving a stream of data bits, characterised by a plurality of shift registers (54) into which samples corresponding to points within said data bit stream are read, different shift registers (54) holding a different set of said samples, said points being separated by most one half of a data bit period, and a decoder (60-90) responsive to said samples held in said shift registers (54) for recognising points of known phase within said data assessed relative to which samples which corresponding to points within said data bits may be identified for reading. The invention provides a high speed serial receiver which is particularly suitable for use within disc drives and data storage and retrieval systems in general. The serial data receiver of the present invention does not require a clock synchronised with the incoming data. Furthermore the serial data receiver is able to share the sampling of the data bit stream between a plurality of shift registers (54) none of which need be clock more than once per data bit period.
Inventors
- 👤 Adrian Charles Frederick Lee
- 👤 Christopher Norman Wallis
- 👤 Philip John Murfet
- 👤 Stephen Furniss
- 👤 Thomas Winlow
- 👤 Michael John Palmer
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 17:22
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/08; H; H03; H03M; H03M9/00; H04; H04L; H04L25/00; H04L25/02; H04L25/06; H04L25/068; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04L7/04; H04L7/041; H04L7/042
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
98 words
An asynchronous serial data receiver for receiving a stream of data bits, characterised by a plurality of shift registers (54) into which samples corresponding to points within said data bit stream are read, different shift registers (54) holding different sets of said samples, said points being separated by at most one half of a data bit period, and a decoder (60-90) responsive to aid samples held in said shift registers (54) for recognising points of known phase within said data assessed relative to which samples which correspond to points within said data bits may be identified for reading.
Claim 2
Dependent Claim
98 words
An asynchronous serial data receiver for receiving a stream of data bits, characterised by a plurality of shift registers (54) into which samples corresponding to points within said data bit stream are read, different shift registers (54) holding different sets of said samples, said points being separated by at most one half of a data bit period, and a decoder (60-90) responsive to aid samples held in said shift registers (54) for recognising points of known phase within said data assessed relative to which samples which correspond to points within said data bits may be identified for reading.
Claim 3
Dependent Claim
23 words
An asynchronous serial data receiver as claimed in claim 1, wherein samples most closely corresponding to midpoints of said data bits are read.
Claim 4
Dependent Claim
47 words
An asynchronous serial data receiver as claimed in claim 1 or 2, wherein said data bit stream is sampled into a sample delay line (2) having a plurality of stages (4), said samples being periodically read from said sample delay line (2) into said shift registers (54).
Claim 5
Dependent Claim
71 words
An asynchronous serial data receiver as claimed in claim 3, further comprising a control delay line (10) having a plurality of stages (4) with a delay matched to that of said sample delay line (2), wherein the delays of both said sample delay line (2) and said control delay line (10) are adjusted by a common feedback signal to phase lock said control delay line (10) to a receiver clock signal.
Claim 6
Dependent Claim
22 words
An asynchronous serial data receiver as claimed in claim 4, wherein said control delay line (10) is configured as a ring oscillator.
Claim 7
Dependent Claim
60 words
An asynchronous serial data receiver as claimed in claim 1 or 2, further comprising a delay line (10) configured as a ring oscillator phase locked to a receiver clock signal, wherein a plurality of timing signals used to control sampling of said data bit stream into said shift registers (54) are derived from differing points along said delay line (10).
Claim 8
Dependent Claim
53 words
An asynchronous serial data receiver as claimed in claim 6, further comprising a plurality of latches (52), wherein each timing signal is fed to a corresponding latch (52) to trigger reading of said data bit stream into said corresponding latch (52), each latch then being read into one of said shift registers (54).
Claim 9
Dependent Claim
85 words
An asynchronous serial data receiver as claimed any of claims 4 to 7, further comprising synchronisation logic (14) responsive to said stages (4) of said control delay line (10), wherein if said synchronisation logic (14) detects more than one pulse propagating along said control delay line (10) then said synchronisation logic produces an adjusting signal which is fed to said control delay line (10) to adjust operation of said control delay line (10) to provide a single pulse propagating along said control delay line (10).
Claim 10
Dependent Claim
54 words
An asynchronous serial data receiver as claimed any of claims 5 to 8, further comprising a ring oscillator frequency divider (48) to provide a reduced frequency signal derived from said ring oscillator prior to comparison with the receiver clock signal, whereby said ring oscillator runs at a higher frequency than said receiver clock signal.
Claim 11
Dependent Claim
45 words
An asynchronous serial data receiver as claimed in claim 9, further comprising a clock frequency divider (50) to provide a reduced frequency signal derived from said receiver clock, whereby the ratio between the frequencies of said ring oscillator and said receiver clock may be varied.
Claim 12
Dependent Claim
37 words
An asynchronous serial data receiver as claimed in any preceding claim, wherein said decoder (60-90) recognises any one of a set of predetermined patterns of samples corresponding to points of known phase within said data bit stream.
Claim 13
Dependent Claim
40 words
An asynchronous serial data receiver as claimed in any preceding claim, wherein said decoder (60-90) recognises a transition within the data bit stream and assesses the samples to be read relative to this transition until the next transition is detected.
Claim 14
Dependent Claim
44 words
An asynchronous serial data receiver as claimed in claim 11 or 12, wherein said patterns recognised by said decoder (60-90) comprise a plurality of samples consistent with a pretransition data stream value and a plurality of samples consistent with a posttransition data stream value.
Claim 15
Dependent Claim
89 words
An asynchronous serial data receiver as claimed in any preceding claim, wherein said decoder (60-90) is arranged such that when a pattern is recognised indicating that the samples to be read correspond to samples different from those currently assessed to be read then said decoder (60-90) changes state to shift the position of those samples assessed to be read towards those assessed relative to said detected point of known phase subject to a predetermined maximum shift which is less than half the number of samples taken per bit period.
Claim 16
Dependent Claim
30 words
An asynchronous serial data receiver as claimed in any preceding claim, wherein said data bit stream is sampled at a rate substantially corresponding to five samples per data bit period.
Claim 17
Dependent Claim
21 words
An asynchronous serial data receiver as claimed in any preceding claim, wherein said samples are decoded once per data bit period.
Claim 18
Dependent Claim
73 words
An asynchronous serial data receiver as claimed in any preceding claim, wherein when said decoder (60-90) recognises a sample pattern indicative of the need to change the sample read from being the first sample in the current period timed by said receiver to being the last sample in the next period to be timed by said receiver, also triggers the reading of the last sample in said current period timed by said receiver.
Claim 19
Dependent Claim
72 words
An asynchronous serial data receiver as claimed in any preceding claim, wherein when said decoder (60-90) recognises a sample pattern indicative of the need to change the sample read from being the last sample in the current period timed by said receiver to being the first sample in the next but one period timed by said receiver also triggers no sample to be read from the next period timed by said receiver.
Claim 20
Dependent Claim
31 words
An asynchronous serial data receiver as claimed in any preceding claim, wherein said shift registers (54) have two stages, each stage holding a sample from adjacent periods timed by said receiver.
Claim 21
Dependent Claim
72 words
An asynchronous serial data receiver as claimed in any preceding claim, wherein bits decoded by said receiver are collected within a bit collection register (92), a counter (94) being arranged to count the number of bits inputted to the bit collection register (92) since said bit collection register (92) was last read and to trigger reading of said bit collection register (92) when an appropriate number of data bits have been decoded.
Claim 22
Dependent Claim
51 words
An asynchronous serial data receiver as claimed in any preceding claim, further comprising a synchronisation word detector (102, 104) for monitoring decoded data bits and providing a synchronisation word signal upon recognition of a synchronisation word, said synchronisation word signal being used to split said decoded data bits into data words.
Claim 23
Independent Claim
77 words
A method of receiving asynchronous serial data characterised by reading a different set of samples corresponding to points within said serial data into different shift registers (54), said points being separated by at most one half of a data bit period, decoding said samples to recognise points of known phase within said data, and assessing said samples relative to said points of known phase to identify for reading samples which corresponding to points within said data bits.
Claim 24
Independent Claim
77 words
A method of receiving asynchronous serial data characterised by reading a different set of samples corresponding to points within said serial data into different shift registers (54), said points being separated by at most one half of a data bit period, decoding said samples to recognise points of known phase within said data, and assessing said samples relative to said points of known phase to identify for reading samples which corresponding to points within said data bits.
Claim 25
Dependent Claim
102 words
A disc drive including an asynchronous serial data receiver for receiving a stream of data bits, characterised by a plurality of shift registers (54) into which samples corresponding to points within said data bit stream are read, different shift registers (54) holding a different set of said samples, said points being separated by most one half of a data bit period, and a decoder (60-90) responsive to said samples held in said shift registers (54) for recognising points of known phase within said data assessed relative to which samples which corresponding to points within said data bits may be identified for reading.
Claim 26
Dependent Claim
102 words
A disc drive including an asynchronous serial data receiver for receiving a stream of data bits, characterised by a plurality of shift registers (54) into which samples corresponding to points within said data bit stream are read, different shift registers (54) holding a different set of said samples, said points being separated by most one half of a data bit period, and a decoder (60-90) responsive to said samples held in said shift registers (54) for recognising points of known phase within said data assessed relative to which samples which corresponding to points within said data bits may be identified for reading.
Claim 27
Dependent Claim
105 words
A data storage and retrieval system including an asynchronous serial data receiver for receiving a stream of data bits, characterised by a plurality of shift registers (54) into which samples corresponding to points within said data bit stream are read, different shift registers (54) holding a different set of said samples, said points being separated by most one half of a data bit period, and a decoder (60-90) responsive to said samples held in said shift registers (54) for recognising points of known phase within said data assessed relative to which samples which corresponding to points within said data bits may be identified for reading.
Claim 28
Dependent Claim
105 words
A data storage and retrieval system including an asynchronous serial data receiver for receiving a stream of data bits, characterised by a plurality of shift registers (54) into which samples corresponding to points within said data bit stream are read, different shift registers (54) holding a different set of said samples, said points being separated by most one half of a data bit period, and a decoder (60-90) responsive to said samples held in said shift registers (54) for recognising points of known phase within said data assessed relative to which samples which corresponding to points within said data bits may be identified for reading.
References Cited (Backward Citations)
No citation records indexed.
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