Logic circuits using a status holding circuit

Claim 2

A status holding circuit comprising: a transistor (14) having an emitter coupled to a negative power source (GND), a collector and a base coupled to said collector and having a negative conductance range; first and second input terminals (A, B) to which first and second input signals are applied; a first resistor (R6) provided between said first input terminal and the collector of said transistor; a second resistor (R5) provided between said second input terminal and the collector of said transistor; and amplifier means (15, R7 - R10) provided between a positive power source (Vcc) and said negative power source, for amplifying an output of said transistor drawn from said base thereof to thereby generate an amplified output signal (Q, 0).

Claim 3

A status holding circuit as claimed in claim 1, characterized in that said transistor (14) is a resonant-tunneling hot electron transistor.

Claim 4

A status holding circuit as claimed in claim 1, characterized in that said transistor (14) is a resonant-tunneling bipolar transistor.

Claim 5

A status holding circuit as claimed in any of claims 1 to 3, characterized in that said amplifier means (15, R7 - R10) comprises a transistor (15) having a base directly connected to the base and collector of said transistor (14) of said status holding circuit, a collector through which said amplified output signal is drawn, and an emitter coupled to said negative power source through an emitter resistor (R7), and the collector of said transistor of said amplifier means is coupled to said positive power source through a load resistor (R8).

Claim 6

A status holding circuit as claimed in any of claims 1 to 3, characterized in that said amplifier means (15, R7 - R10) comprises a transistor (15) having a base connected to the base and collector of said transistor (14) of said status holding circuit through a third resistor (R9) and coupled to said negative power source through a fourth resistor (R10), a collector through which said amplified output signal is drawn, and an emitter directly connected to said negative power source, and the collector of said transistor of said amplifier means is coupled to said positive power source through a load resistor (R8).

Claim 7

A status holding circuit as claimed in claim 5, characterized in that said transistor (15) of said amplifier means is a transistor selected from the group consisting of a resonant-tunneling hot electron transistor, a resonant-tunneling bipolar transistor and a normal bipolar transistor.

Claim 8

A status holding circuit as claimed in claim 5, characterized in that said transistor (14) of said status holding circuit is of the same type as said transistor (15) of said amplifier means.

Claim 9

A status holding circuit as claimed in any of claims 1 to 7, characterized in that when the first and second input signals (A, B) are both logic "0" said output signal is logic "0", and when the first and second input signals are both logic "1" said output signal is logic "1", and in that one of said first and second input signals is logic "0" and the other input signal is logic "1", the output signal obtained at this time is the same as the previous status of the output signal.

Claim 10

A status holding circuit as claimed in any of claims 1 to 8, characterized by further comprising an emitter follower transistor (16) having a base provided with said amplified output signal, a collector coupled to said positive power source, and an emitter through which said amplified output signal is drawn.

Claim 11

A status holding circuit as claimed in any of claims 1 to 9, characterized in that the resistance of said first resistor (R6) is the same as that of said second resistor (R5).

Claim 12

A logic circuit comprising: an exclusive-OR gate (11) having first and second input terminals and an output terminal, a first input signal (C) being applied to said first input terminal; and a status holding circuit (2, 12) coupled to said exclusive-OR gate, said status holding circuit including: a transistor (14) having an emitter coupled to a negative power source (GND), a collector and a base coupled to said collector and having a negative conductance range; a first input terminal (A) coupled to the output terminal of said exclusive-OR gate; a second input terminal (B) to which a second input signal (D) is applied; a first resistor (R6) provided between said first input terminal (A) of said status holding circuit and the collector of said transistor; a second resistor (R5) provided between said second input terminal (B) of said status holding circuit and the collector of said transistor; and amplifier means (15, R7 - R10) provided between a positive power source (Vcc) and said negative power source, for amplifying an output of said transistor drawn from said base thereof to thereby generate an amplified output signal (Q, 0), which is applied to the second input terminal of said exclusive-OR gate (11).

Claim 13

A logic circuit comprising: an exclusive-OR gate (11) having first and second input terminals and an output terminal, a first input signal (C) being applied to said first input terminal; and a status holding circuit (2, 12) coupled to said exclusive-OR gate, said status holding circuit including: a transistor (14) having an emitter coupled to a negative power source (GND), a collector and a base coupled to said collector and having a negative conductance range; a first input terminal (A) coupled to the output terminal of said exclusive-OR gate; a second input terminal (B) to which a second input signal (D) is applied; a first resistor (R6) provided between said first input terminal (A) of said status holding circuit and the collector of said transistor; a second resistor (R5) provided between said second input terminal (B) of said status holding circuit and the collector of said transistor; and amplifier means (15, R7 - R10) provided between a positive power source (Vcc) and said negative power source, for amplifying an output of said transistor drawn from said base thereof to thereby generate an amplified output signal (Q, 0), which is applied to the second input terminal of said exclusive-OR gate (11).

Claim 14

A logic circuit as claimed in claim 11, characterized by further comprising a NOT gate (1a) coupled to the output terminal of said exclusive-OR gate (1), wherein the first input terminal (A) of said status holding circuit (2, 12) is coupled to the output terminal of said exclusive-OR gate through said NOT gate so that an exclusive-NOR gate (11) is configured by said exclusive-OR gate and said NOT gate.

Claim 15

A logic circuit as claimed in claim 12, characterized in that said exclusive-NOR gate (11) comprises a transistor (13) having an emitter coupled to said negative power source (GND), a base coupled to said first input terminal of said exclusive-OR gate through a third resistor (R1) and coupled to said negative power source through a fourth resistor (R3), and a collector connected to said first input terminal (A) of said status holding circuit (12) and coupled to said positive power source (Vcc) through a fifth resistor (R4), and in that the base of said transistor (13) of said exclusive-NOR gate is provided with said amplified output through a sixth resistor (R2).

Claim 16

A logic circuit as claimed in claim 13, characterized in that said third and sixth resistors (R1, R2) of said exclusive-NOR gate (11) have the same resistance.

Claim 17

A logic circuit as claimed in claim 13, characterized in that said two transistors (13, 14) respectively provided in said exclusive-NOR gate (11) and said status holding circuit (12) are resonant-tunneling hot electron transistors.

Claim 18

A logic circuit as claimed in claim 13, characterized in that said two transistors (13, 14) respectively provided in said exclusive-NOR gate (11) and said status holding circuit (12) are resonant-tunneling bipolar transistors.

Claim 19

A logic circuit as claimed in any of claims 11 to 16, characterized in that the resistance of each of said third and sixth resistors (R1, R2) is smaller than an input resistance of said transistor (13) of said exclusive-NOR circuit (11).

Claim 20

A logic circuit as claimed in any of claims 11 to 17, characterized in that said amplifier means (15, R7 - R10) comprises a transistor (15) having a base directly connected to the base and collector of said transistor (14) of said status holding circuit (12), a collector through which said amplified output signal is drawn, and an emitter coupled to said negative power source through an emitter resistor (R7), and the collector of said transistor (15) of said amplifier means is coupled to said positive power source (Vcc) through a load resistor (R8).

Claim 21

A logic circuit as claimed in claim 18, characterized in that said amplifier means (15, R7 -R10) comprises a transistor (15) having a base connected to the base and collector of said transistor (14) of said status holding circuit through a seventh resistor (R9) and coupled to said negative power source (GND) through an eighth resistor (R10), a collector through which said amplified output signal is drawn, and an emitter directly connected to said negative power source, and the collector of said transistor of said amplifier means is coupled to said positive power source through a load resistor (R8).

Claim 22

A logic circuit as claimed in any of claims 11 to 19, characterized in that said first input signal (C) is a clock signal and said second input signal (D) is data signal to be held by said status holding circuit (2, 12) in accordance with said first input signal.

Claim 23

A logic circuit as claimed in claim 20, characterized in that when said clock signal (C) is logic "0", there is no change in said amplified output irrespective of said data signal (D), and when said clock signal is logic "1", said amplified output signal obtained at this time is the same as said data signal.

Claim 24

A logic circuit as claimed in any of claims 11 to 19, characterized by further comprising an emitter follower transistor (16) having a base provided with said amplified output signal, a collector coupled to said positive power source (Vcc), and an emitter through which said amplified output signal is drawn.

Claim 25

A logic circuit as claimed in claim 19, characterized in that each of said transistors (13, 14, 15) provided in said exclusive-NOR gate, said status holding circuit and said amplifier means is of the same type.

Claim 26

A logic circuit comprising: an exclusive-OR gate (1) having a first input terminal to which a clock signal (C) is applied, a second input terminal and an output terminal; and a status holding circuit (2) having a first input terminal (A) coupled to the output terminal of said exclusive-OR gate, a second input terminal (B) to which a data signal (D) is applied, and an output terminal coupled to the second input terminal of said exclusive-OR gate, an output signal (Q) being drawn from the output terminal of said status holding circuit, said status holding circuit having a hysteresis characteristic, wherein when said clock signal is logic "0", there is no change in said output signal irrespective of said data signal, and when said clock signal is logic "1", said output signal obtained at this time is the same as said data signal.

Claim 27

A logic circuit comprising: an exclusive-OR gate (1) having a first input terminal to which a clock signal (C) is applied, a second input terminal and an output terminal; and a status holding circuit (2) having a first input terminal (A) coupled to the output terminal of said exclusive-OR gate, a second input terminal (B) to which a data signal (D) is applied, and an output terminal coupled to the second input terminal of said exclusive-OR gate, an output signal (Q) being drawn from the output terminal of said status holding circuit, said status holding circuit having a hysteresis characteristic, wherein when said clock signal is logic "0", there is no change in said output signal irrespective of said data signal, and when said clock signal is logic "1", said output signal obtained at this time is the same as said data signal.

Claim 28

A logic circuit comprising: an exclusive-NOR gate (11) having a first input terminal to which a clock signal (C) is applied, a second input terminal and an output terminal; and a status holding circuit (12) having a first input terminal (A) coupled to the output terminal of said exclusive-OR gate, a second input terminal (B) to which a data signal (D) is applied, and an output terminal coupled to the second input terminal of said exclusive-OR gate, an output signal ( being drawn from the output terminal of said status holding circuit, said status holding circuit having a hysteresis characteristic, wherein when said clock signal is logic "0", there is no change in said output signal irrespective of said data signal, and when said clock signal is logic "1", said output signal obtained at this time is an inverted signal of said data signal.

Claim 29

A logic circuit comprising: an exclusive-NOR gate (11) having a first input terminal to which a clock signal (C) is applied, a second input terminal and an output terminal; and a status holding circuit (12) having a first input terminal (A) coupled to the output terminal of said exclusive-OR gate, a second input terminal (B) to which a data signal (D) is applied, and an output terminal coupled to the second input terminal of said exclusive-OR gate, an output signal ( being drawn from the output terminal of said status holding circuit, said status holding circuit having a hysteresis characteristic, wherein when said clock signal is logic "0", there is no change in said output signal irrespective of said data signal, and when said clock signal is logic "1", said output signal obtained at this time is an inverted signal of said data signal.