Patent EP0388300A2 successfully refreshed from Google Patents.
EP0388300A2
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EP
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Controller for direct memory access
Assignee: Micral Inc
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Filing: 1990-03-14
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Granted: —
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Expires: 2010-03-14
Abstract
Abstract A direct memory access controller for computer systems in which the data may be manipulated and acted upon during a transfer to and from locations in memory, or from locations in memory to and from input/output devices. For computer systems having data word widths of two or more bytes of data fewer bus cycles are required for data transfers to and from odd address locations in memory.
Inventors
- 👤 Richard M. Mansfield
- 👤 William F. Dohse
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 05:50
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
73 words
In a computer system having data storage means and input/output devices coupled thereto, a direct memory access system comprising: transfer means for transferring data to and from locations in said data storage means and for transferring data from locations in said data storage means to and from said input/output devices via a data bus having data bus cycles; and, manipulator means coupled to the transfer means for manipulating the data during said transfers.
Claim 2
Dependent Claim
73 words
In a computer system having data storage means and input/output devices coupled thereto, a direct memory access system comprising: transfer means for transferring data to and from locations in said data storage means and for transferring data from locations in said data storage means to and from said input/output devices via a data bus having data bus cycles; and, manipulator means coupled to the transfer means for manipulating the data during said transfers.
Claim 3
Dependent Claim
24 words
A direct memory access system as in Claim 1 wherein said manipulator controls the number of data bus cycles required for transfer of data.
Claim 4
Dependent Claim
25 words
A direct memory access system as in Claim 1 wherein said manipulator means further includes sorter means for controlling the sequence of data being transferred.
Claim 5
Dependent Claim
34 words
A direct memory access system as in Claim 1 wherein said manipulator means further includes latch means, coupled to said transfer means and to said sorter means for receiving and transmitting data being transferred.
Claim 6
Dependent Claim
38 words
A direct memory access system as in Claim 1 wherein said manipulator means further includes data pre-processor means, coupled to said sorter means and to said transfer means for performing arithmetic and logical operations on data being transferred.
Claim 7
Dependent Claim
23 words
A direct memory access system as in Claim 2 wherein said sorter means performs operations on the data being transferred during said transfers.
Claim 8
Dependent Claim
20 words
A direct memory access system as in Claim 6 wherein said operations include controlling the amount of data being transferred.
Claim 9
Dependent Claim
75 words
A direct memory access system as in Claim 2 wherein: said data includes words of data, each word comprising a plurality of bytes and having a word address; said locations have odd and even byte addresses for storing bytes of data thereat; and, said manipulator means controls transfer of data to and from locations having odd word addresses in 2N + 1 bus cycles, where N is the number of words of data being transferred.
Claim 10
Dependent Claim
58 words
A direct memory access system as in Claim 8 wherein said manipulator means includes: first selector means for selecting the word address of the data being transferred; second selector means for selecting the byte address of the data being transferred; said first selector means being effective for decrementing and incrementing the word address of the data being transferred.
Claim 11
Dependent Claim
50 words
A direct memory access system as in Claim 2 wherein: said data is organized into words, each word having a plurality of bytes and having a word address; and each transfer of data words comprises one bus cycle for a read operation and one bus cycle for a write operation.
Claim 12
Dependent Claim
39 words
A direct memory access system as in Claim 10 wherein: said locations having odd and even byte and word address; and each transfer of one or more data words from an odd word address requires one additional bus cycle.
Claim 13
Dependent Claim
22 words
A direct memory access system as in Claim 10 wherein said manipulator means manipulates data being transferred between read and write operations.
Claim 14
Dependent Claim
31 words
A direct memory access system as in Claim 10 wherein the read operation for a data word being transferred occurs concurrently with the write operation for the data word previously read.
References Cited (Backward Citations)
No citation records indexed.
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