Abstract A multiprocessor system in which a plurality of processors are connected to a shared bus and a shared memory through private caches and in which access to the shared bus is monitored to process data in the private caches in accordance with a specified protocol, the multiprocessor system further comprising a protocol bus carrying protocol signals signifying a current one of a plurality of possible protocols, and cache control mechanisms connected in common to the protocol bus and individually effective for and on each private cache; each control mechanism comprising: protocol memory means storing an indication of the current protocol specified for identifiable data memory areas controlled thereby, protocol signal generating means for reading, from the protocol memory means when data is accessed, the protocol of the memory area to which the accessed data belongs and broadcasting a corresponding protocol signal on the protocol bus, and detecting means for detecting protocol signals on the protocol bus and causing the data in the corresponding private cache to be processed under the protocol specified thereby. A processor group bus for broadcasting processor group signals specifying various groups of processors the members of which are to observe a specified protocol can also be provided.
A multiprocessor system in which a plurality of processors are connected to a shared bus and a shared memory through private caches and in which access to the shared bus is monitored to process data in the private caches in accordance with a specified protocol, the multiprocessor system further comprising: a protocol bus carrying protocol signals signifying a current one of a plurality of possible protocols, and cache control mechanisms connected in common to the protocol bus and individually effective for and on each private cache; each control mechanism comprising: protocol memory means storing an indication of the current protocol specified for identifiable data memory areas controlled thereby, protocol signal generating means for reading, from the protocol memory means when data is accessed, the protocol of the memory area to which the accessed data belongs and broadcasting a corresponding protocol signal on the protocol bus, and detecting means for detecting protocol signals on the protocol bus and causing the data in the corresponding private cache to be processed under the protocol specified thereby.
Claim 2
Dependent Claim
173 words
A multiprocessor system in which a plurality of processors are connected to a shared bus and a shared memory through private caches and in which access to the shared bus is monitored to process data in the private caches in accordance with a specified protocol, the multiprocessor system further comprising: a protocol bus carrying protocol signals signifying a current one of a plurality of possible protocols, and cache control mechanisms connected in common to the protocol bus and individually effective for and on each private cache; each control mechanism comprising: protocol memory means storing an indication of the current protocol specified for identifiable data memory areas controlled thereby, protocol signal generating means for reading, from the protocol memory means when data is accessed, the protocol of the memory area to which the accessed data belongs and broadcasting a corresponding protocol signal on the protocol bus, and detecting means for detecting protocol signals on the protocol bus and causing the data in the corresponding private cache to be processed under the protocol specified thereby.
Claim 3
Dependent Claim
20 words
A multiprocessor system as claimed in Claim 1, in which the unit of the data memory area is a page.
Claim 4
Dependent Claim
28 words
A multiprocessor system as claimed in Claim 2, in which the protocol memory means and protocol signal generating means are embodied in the corresponding cache page control mechanism.
Claim 5
Dependent Claim
118 words
A multiprocessor system as claimed in any preceding claim, further including a processor group bus for broadcasting processor group signals specifying various groups of processors the members of which are to observe a specified protocol, the cache control mechanisms being connected in common to the processor group bus and including; a processor group signal generating means for transmitting the processor group signal to the processor group bus when the protocol type signal represents the protocol type which limits effective processors, and grouping means for detecting processor group signals on the processor group bus to determine whether or not the associated processor grouping to which the currently specified protocol is to apply contains the associated cache/processor, applying control accordingly.
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