Storage control in cached multi-processor systems

Abstract

Abstract A multiprocessor system in which a plurality of processors are connected to a shared bus and a shared memory through private caches and in which access to the shared bus is monitored to process data in the private caches in accordance with a specified protocol, the multiprocessor system further comprising a protocol bus carrying protocol signals signifying a current one of a plurality of possible protocols, and cache control mechanisms connected in common to the protocol bus and individually effective for and on each private cache; each control mechanism comprising: protocol memory means storing an indication of the current protocol specified for identifiable data memory areas controlled thereby, protocol signal generating means for reading, from the protocol memory means when data is accessed, the protocol of the memory area to which the accessed data belongs and broadcasting a corresponding protocol signal on the protocol bus, and detecting means for detecting protocol signals on the protocol bus and causing the data in the corresponding private cache to be processed under the protocol specified thereby. A processor group bus for broadcasting processor group signals specifying various groups of processors the members of which are to observe a specified protocol can also be provided.

Inventors

• 👤 Takashi Coop Sunshaine 203Goh Matsumoto

Bibliographic Details