Codable electronic devices, e.g. transponders

Claim 2

A codable electronic device comprising input circuitry (400) and data storage means (SR1, SR2, SR3,520), the input circuitry being arranged to receive pulses of a carrier signal and comprising means (134) for providing a logic signal (A o , Q (B) ) in response to the pulses, characterised in that the logic value of the logic signal (A o , Q (B) ) is dependent upon the length of a respective incoming carrier pulse, and in that means (440,405;520) are provided for preventing said logic value being supplied to the data storage means until termination of said pulse.

Claim 3

A device according to claim 1, wherein the data storage means comprises a main memory (SR1) of the device, the means providing the logic signal (A o ) thereto comprises a divider chain (134), and the preventing means is a reset output (440) of the input circuitry (400), the output (440) being connected to a memory input (CLOCK) which clocks data into the memory (SR1).

Claim 4

A device according to claim 1, wherein the data storage means comprises means (SR2, SR3, 520) for changing the functioning of the device, wherein the means providing the logic signal (A o , Q (B) ) thereto comprises a divider chain (134), and wherein the preventing means is a reset output (440) of the input circuitry (400), the output (440) being connected to an input (R) which clocks data into the data storage means (SR2, SR3, 520).

Claim 6

A device according to claim 4, wherein, upon the occurrence of matching, the key (403) enables a latch circuit (404) which opens an AND-gate (405) to pass signals from the reset output (440) to the clock input (CLOCK) of the main memory (SR1), the device further comprising means (407) for producing a delayed reset signal (R D ) if the time between successive carrier pulses exceeds a predetermined maximum value which resets the functioning changing means (SR2) and the latch circuit (404), and means (A₁) for resetting the functioning changing means (SR2) if the duration of a carrier pulse exceeds a predetermined maximum value.

Claim 8

A device according to claim 6, wherein, upon the occurrence of matching, the key (503) enables a latch circuit (500) which opens an AND-gate (510) to pass signals from input circuitry (400) to a device output (410).

Claim 9

A device according to claim 3, wherein the data storage means comprises a first flip-flop (520), wherein the means providing the logic signal (Q (B) ) thereto comprises a second flip-flop (530) which receives as a clocking input thereto a signal (X) from said divider chain (134), and wherein, upon receipt of a carrier pulse having a satisfactory length, the first flip-flop (520) actuates means to permit the device to respond to an interrogation pulse transmitted thereto.

Claim 10

A device according to claim 8 wherein the first flip-flop (520) has means for applying a resetting signal (R (A) ) thereto a predetermined period after the termination of a carrier pulse unless it is followed, within said period, by an interrogation pulse.

Claim 13

A codable electronic device comprising input circuitry (400) and data storage means (SR1, SR2, SR3, 520), the input being arranged to receive pulses of a carrier signal and comprising means (134) for providing a logic signal (A o , (Q (B) ) in response to the pulses, characterised in that the logic value of the logic signal (A o , (Q (B) ) is dependent upon the length of a respective incoming carrier pulse.

Claim 14

A codable electronic device comprising input circuitry (400) and data storage means (SR1, SR2, SR3, 520), the input being arranged to receive pulses of a carrier signal and comprising means (134) for providing a logic signal (A o , (Q (B) ) in response to the pulses, characterised in that the logic value of the logic signal (A o , (Q (B) ) is dependent upon the length of a respective incoming carrier pulse.

Claim 15

A codable electronic device comprising input circuitry (400) and data storage means (SR1, SR2, SR3, 520), the input being arranged to receive pulses of a carrier signal and comprising means (134) for providing a logic signal (A o , (Q (B) ) in response to the pulses, characterised in that means are provided for preventing a particular value of the logic signal (A o , (Q (B) ) being supplied to the date storage means until termination of a said pulse.

Claim 16

A codable electronic device comprising input circuitry (400) and data storage means (SR1, SR2, SR3, 520), the input being arranged to receive pulses of a carrier signal and comprising means (134) for providing a logic signal (A o , (Q (B) ) in response to the pulses, characterised in that means are provided for preventing a particular value of the logic signal (A o , (Q (B) ) being supplied to the date storage means until termination of a said pulse.