Serial testing technique for embedded memories

Claim 2

A memory test circuit capable of testing at least one random access memory circuit, that at least one random access memory circuit being adapted to be embedded on a chip and having an aggregate of 'N' data input lines and 'N' data output lines, each memory circuit of the at least one memory circuit sharing the same 'M' address lines and 'P' read/write control lines during testing, the memory test circuit comprising: (a) a finite state machine means adapted to sequence through a series of states for testing the at least one memory circuit; (b) a first multiplexer assembly adapted to be embedded on the chip and having a series of 'N' first inputs and a series of 'N' second inputs, the state of a testing control line on the finite state machine means determining which of the two series of 'N' inputs is connected to a series of 'N' outputs on the first multiplexer assembly, each of the first multiplexer assembly outputs being adapted to be connected to a respective one of the data input lines on the at least one memory circuit, those first inputs on the first multiplexer assembly that are connectable to the data input lines '2' to 'N' on the at least one memory circuit being adapted to be connected to the data output lines '1' to 'N-1', respectively, on the at least one memory circuit, the first input on the first multiplexer assembly that is connectable with data input line '1' on the at least one memory circuit being adapted to be connected to a data output port on the finite state machine means, data output line 'N' on the at least one memory circuit being adapted to be connected to a data input port on the finite state machine means, the series of second inputs on the first multiplexer assembly and the data output lines on the at least one memory circuit being adapted to be connected to a data bus on the chip for non-test operation of the at least one memory circuit; (c) an addressing assembly having a series of 'M' outputs each connected to a respective one of the 'M' address lines on the at least one memory circuit, the addressing assembly having a series of first inputs adapted to be connected to the finite state machine means and having a series of second inputs adapted to be connected to a bus on the chip, the testing control line being connected to the addressing assembly, the state of the testing control line determining whether the series of first inputs or the series of second inputs on the addressing assembly determines the state of the 'M' outputs on the addressing assembly; and, (d) a read/write control assembly having a series of 'P' outputs each connected to a respective one of the 'P' read/write control lines on the at least one random access memory circuit, the read/write control assembly having a series of first inputs adapted to be connected to the finite state machine means and having a series of second inputs adapted to be connected to a control bus on the chip, the testing control line being connected to the read/write control assembly, the state of the testing control line determining whether the series of first inputs or the series of second inputs on the read/write control assembly determines the state of the 'P' outputs of the read/write control assembly; whereby, for purposes of testing the at least one memory circuit, the finite state machine means actuates the testing control line such that the 'N' first inputs on the first multiplexer assembly are the outputs on that assembly and such that the state of the first inputs on the addressing and read/write control assemblies determine the state of the 'M+P' outputs on those assemblies, the finite state machine means during such actuation applying each of the possible addresses to the at least one memory circuit and during the application of each address repeatedly performing the steps of applying a test bit to the data output port, performing a read operation, and performing a write operation, the three steps being repeated at each address a number of times sufficient for the finite state machine means to determine from the test bits received on the data input port whether the at least one memory circuit is defective.

Claim 3

A memory test circuit capable of testing at least one random access memory circuit, that at least one random access memory circuit being adapted to be embedded on a chip, the 'i'th memory circuit having 'N i ' data input lines, 'N i ' data output lines, 'M i ' address lines, and 'P' read/write control lines, the memory test circuit comprising: (a) a finite state machine means adapted to sequence through a series of states for testing the at least one memory circuit; (b) a memory circuit selection means actuated by the finite state machine means; (c) a finite state machine input selection means having a series of inputs each adapted to connect to the final data output line of a respective one of the memory circuits, and having an output adapted to connect to the input port on the finite state machine, the memory circuit selection means determining which of the inputs of the finite state machine input selection means is connected to the output; (d) a first multiplexer assembly adapted to be embedded on the chip for each memory circuit, the first multiplexer assembly for the 'i' th memory circuit having a series of 'N i ' first inputs and a series of 'N i ' second inputs, the state of a testing control line on the finite state machine means determining which of the two series of 'N i ' inputs is connected to a series of 'N i ' outputs on the first multiplexer assembly, each of the first multiplexer assembly outputs on the 'i'th memory circuit being adapted to be connected to a respective one of the data input lines on the 'i'th memory circuit, those first inputs on the first multiplexer assembly that are connectable to the data input lines '2' to 'N i ' on the 'i' th memory circuit being adapted to be connected to the data output lines '1' to 'N i -1', respectively, on the 'i'th memory circuit, the first input on the first multiplexer assembly that is connectable with data input line '1' on each of the memory circuits being adapted to be connected to a data output port on the finite state machine means, the final data output line on each of the memory circuits being adapted to be connected to a respective input of the finite state machine input selection means, the series of second inputs on each first multiplexer assembly of the 'i'th memory circuit and the data output lines on the 'i'th memory circuit being adapted to be connected to a data bus associated with the 'i'th memory circuit on the chip for non-test operation of the 'i'th memory circuit; (e) an addressing assembly having a series of outputs, the number of outputs being at least equal to the number of address lines on that memory circuit of the at least one memory circuit that has the greatest number of address lines, 'M i ' outputs of the addressing assembly being connected to a respective one of the 'M i ' address lines on the 'i'th memory circuit, the memory circuit selection means being connected to the addressing assembly for indicating to the addressing assembly the number of addresses present in each of the memory circuits, the addressing assembly having a series of first inputs adapted to be connected to the finite state machine means and having a series of second inputs adapted to be connected to a bus on the chip, the testing control line being connected to the addressing assembly, the state of the testing control line determining whether the series of first inputs or the series of second inputs on the addressing assembly determines the state of the outputs on the addressing assembly; (f) a read/write control assembly having a series of 'P' outputs each connected to a respective one of the 'P' read/write control lines on the at least one memory circuit, the read/write control assembly having a series of first inputs adapted to be connected to the finite state machine means and having a series of second inputs adapted to be connected to a control bus on the chip, the testing control line being connected to the read/write control assembly, the state of the testing control line determining whether the series of first inputs or the series of second inputs on the read/write control assembly determines the state of the 'P' outputs of the read/write control assembly; whereby, for purposes of testing the at least one memory circuit, the finite state machine means actuates the testing control line such that the first inputs on the first multiplexer assembly of each memory circuit are the outputs on that assembly and such that the first inputs on the addressing and read/write control assemblies determine the state of the outputs on those assemblies, the finite state machine means during each such actuation of the testing control line performing the primary steps for each memory circuit of, firstly, actuating the memory circuit selection means to connect the final data output line of the particular memory circuit to the data input port of the finite state machine means and to send information on the particular memory circuit to the addressing assembly and finite state machine means, secondly, applying each of the possible addresses to the particular memory circuit, and thirdly, for each of the applied addresses repeatedly performing the secondary steps of applying a test bit to the data output port, performing a read operation, and performing a write operation, the primary and secondary steps being repeated a number of times sufficient for the finite state machine means to determine from the test bits received on the data input port whether the at least one memory circuit is defective.

Claim 4

A memory test circuit capable of testing at least one random access memory circuit, that at least one random access memory circuit being adapted to be embedded on a chip, the 'i'th memory circuit having 'N i ' data input lines, 'N i ' data output lines, 'M i ' address lines, and 'P' read/write control lines, the memory test circuit comprising: (a) a finite state machine means adapted to sequence through a series of states for testing the at least one memory circuit; (b) a memory circuit selection means actuated by the finite state machine means; (c) a finite state machine input selection means having a series of inputs each adapted to connect to the final data output line of a respective one of the memory circuits, and having an output adapted to connect to the input port on the finite state machine, the memory circuit selection means determining which of the inputs of the finite state machine input selection means is connected to the output; (d) a first multiplexer assembly adapted to be embedded on the chip for each memory circuit, the first multiplexer assembly for the 'i' th memory circuit having a series of 'N i ' first inputs and a series of 'N i ' second inputs, the state of a testing control line on the finite state machine means determining which of the two series of 'N i ' inputs is connected to a series of 'N i ' outputs on the first multiplexer assembly, each of the first multiplexer assembly outputs on the 'i'th memory circuit being adapted to be connected to a respective one of the data input lines on the 'i'th memory circuit, those first inputs on the first multiplexer assembly that are connectable to the data input lines '2' to 'N i ' on the 'i' th memory circuit being adapted to be connected to the data output lines '1' to 'N i -1', respectively, on the 'i'th memory circuit, the first input on the first multiplexer assembly that is connectable with data input line '1' on each of the memory circuits being adapted to be connected to a data output port on the finite state machine means, the final data output line on each of the memory circuits being adapted to be connected to a respective input of the finite state machine input selection means, the series of second inputs on each first multiplexer assembly of the 'i'th memory circuit and the data output lines on the 'i'th memory circuit being adapted to be connected to a data bus associated with the 'i'th memory circuit on the chip for non-test operation of the 'i'th memory circuit; (e) an addressing assembly having a series of outputs, the number of outputs being at least equal to the number of address lines on that memory circuit of the at least one memory circuit that has the greatest number of address lines, 'M i ' outputs of the addressing assembly being connected to a respective one of the 'M i ' address lines on the 'i'th memory circuit, the memory circuit selection means being connected to the addressing assembly for indicating to the addressing assembly the number of addresses present in each of the memory circuits, the addressing assembly having a series of first inputs adapted to be connected to the finite state machine means and having a series of second inputs adapted to be connected to a bus on the chip, the testing control line being connected to the addressing assembly, the state of the testing control line determining whether the series of first inputs or the series of second inputs on the addressing assembly determines the state of the outputs on the addressing assembly; (f) a read/write control assembly having a series of 'P' outputs each connected to a respective one of the 'P' read/write control lines on the at least one memory circuit, the read/write control assembly having a series of first inputs adapted to be connected to the finite state machine means and having a series of second inputs adapted to be connected to a control bus on the chip, the testing control line being connected to the read/write control assembly, the state of the testing control line determining whether the series of first inputs or the series of second inputs on the read/write control assembly determines the state of the 'P' outputs of the read/write control assembly; whereby, for purposes of testing the at least one memory circuit, the finite state machine means actuates the testing control line such that the first inputs on the first multiplexer assembly of each memory circuit are the outputs on that assembly and such that the first inputs on the addressing and read/write control assemblies determine the state of the outputs on those assemblies, the finite state machine means during each such actuation of the testing control line performing the primary steps for each memory circuit of, firstly, actuating the memory circuit selection means to connect the final data output line of the particular memory circuit to the data input port of the finite state machine means and to send information on the particular memory circuit to the addressing assembly and finite state machine means, secondly, applying each of the possible addresses to the particular memory circuit, and thirdly, for each of the applied addresses repeatedly performing the secondary steps of applying a test bit to the data output port, performing a read operation, and performing a write operation, the primary and secondary steps being repeated a number of times sufficient for the finite state machine means to determine from the test bits received on the data input port whether the at least one memory circuit is defective.

Claim 5

A memory test circuit as in claim 1 or 2, wherein the addressing assembly comprises a counter means.

Claim 6

A memory test circuit as in claim 1 or 2, wherein the addressing assembly comprises a counter means and a second multiplexer assembly, the series of first inputs on the addressing assembly being inputs to the counter means, the series of outputs on the addressing assembly being the outputs of the second multiplexer assembly, a series of outputs from the counter means being connected to a respective one of a series of first inputs on the second multiplexer assembly, the series of second inputs on the addressing assembly being a series of second inputs on the second multiplexer assembly which are adapted to be connected to an address bus on the chip, the testing control line being connected to the second multiplexer assembly, the state of the testing control line determining which of the series of first and second inputs on the second multiplexer assembly are connected to the address lines on the at least one memory circuit.

Claim 7

A memory test circuit as in claim 4, wherein the read/write control assembly comprises a timing generator means and a third multiplexer assembly, the series of first inputs on the read/write control assembly being inputs to the timing generator means, the series of outputs on the read/write control assembly being the outputs of the third multiplexer assembly, a series of outputs from the timing generator means being connected to a respective one of a series of first inputs on the third multiplexer assembly, the series of second inputs of the read/write control assembly being a series of second inputs on the third multiplexer assembly which are adapted to be connected to a control bus on the chip, the testing control line being connected to the third multiplexer assembly, the state of the testing control line determining which of the series of first and second inputs on the third multiplexer assembly are connected to the read/write control lines on the at least one memory circuit.

Claim 8

A memory test circuit as in claim 1, wherein the addressing assembly and the read/write control assembly are adapted to be embedded on the same chip on which the at least one random access memory circuit is adapted to be embedded.

Claim 9

A memory test circuit as in claim 6, wherein the finite state machine means counter unit is also adapted to be embedded on the same chip on which the at least one random access memory circuit is adapted to be embedded.

Claim 10

A memory test circuit as in claim 5, wherein the second and third multiplexer assemblies are adapted to be embedded on the same chip on which the at least one random access memory circuit is adapted to be embedded.

Claim 11

A memory test circuit capable of testing at least one random access memory circuit, that at least one random access memory circuit being adapted to be embedded on a chip and having address lines, read/write control lines, and separated data input and data output lines, the memory test circuit comprising: (a) a finite state machine means adapted to sequence through a series of states for testing the at least one memory circuit; (b) a counter means, the counter means being connected to the finite state machine means and having a series of output lines equal in number to the number of address lines on the at least one random access memory circuit; (c) a timing generator means, the timing generator means being connected to the finite state machine means and having series of output lines equal in number to the number of read/write control lines on the at least one random access memory circuit; (d) a series of two-input first multiplexer units adapted to be embedded on the chip, the number of first multiplexer units being equal to the total number of data input lines on the at least one memory circuit, those input lines each being associated with a respective one of a series of consecutive bit positions together representing a row addressed in the at least one memory circuit, the output line of each first multiplexer unit being adapted to be connected to a respective one of the data input lines on the at least one memory circuit, a first input line on each first multiplexer unit with the exception of that first multiplexer unit which is associated with the first position being adapted to be connected to the data output line of the consecutive bit position on the at least one memory circuit, the first input line on that first multiplexer unit which is associated with the first bit position being adapted to be connected to a data output port on the finite state machine means, the data output line at the final bit position of the at least one memory circuit being adapted to be connected to a data input port on the finite state machine means, the second input line on each first multiplexer unit being adapted to be connected to a respective one of the lines of a data bus on the chip for sending parallel data to the at least one memory circuit during non-test operation, the data output lines being adapted to be connected to a respective one of the lines of the data bus for receiving parallel data from the at least one memory circuit during non-test operation, the finite state machine means being adapted to be connected to a testing control line on the series of first multiplexer units for selecting whether the data input lines on the at least one memory circuit are connected to either all of the first input lines or all of the second input lines on the first multiplexer units; (e) a series of two-input second multiplexer units adapted to be embedded on the chip, the number of second multiplexer units being equal to the total number of address lines on the at least one memory circuit, the output line of each second multiplexer unit being adapted to be connected to a respective one of those address lines, a first input line of each second multiplexer unit being adapted to be connected to the counter means, a second input line of each second multiplexer unit being adapted to be connected to a respective one of the address lines on the chip for providing address signals to the at least one memory circuit during non-test operation, the testing control line being adapted to be connected to the series of second multiplexer units for selecting whether the address lines of the at least one memory circuit are connected to either all of the first input lines or all of the second input lines on the second multiplexer units; and, (f) a series of two-input third multiplexer units adapted to be embedded on the chip, the number of third multiplexer units being equal to the total number of read/write control lines on the at least one memory circuit, the output line of each third multiplexer unit being adapted to be connected to a respective one of those read/write control lines, a first input line of each third multiplexer unit being adapted to be connected to the timing generator means, a second input line of each third multiplexer unit being adapted to be connected to a respective one of the read/write control lines on the chip for providing read/write control signals to the at least one memory circuit during non-test operation, the testing control line being adapted to be connected to the series of third multiplexer units for selecting whether the read/write control lines of the at least one memory circuit are connected to either all of the first input lines or all of the second input lines on the third multiplexer units; whereby, for purposes of testing the at least one memory circuit, the finite state machine means actuates the testing control line such that the first input lines of the first, second and third multiplexer units are interfaced to the at least one memory circuit, the finite state machine means during such actuation applying each of the possible addresses to the at least one memory circuit and during the application of each address repeatedly performing the steps of applying a test bit to the first input of the first multiplexer unit at the first bit position of the at least one memory circuit, performing a read operation, and performing a write operation, the three steps being repeated at each address a number of times sufficient for the finite state machine means to determine from the test bits received on the data input port whether the at least one memory circuit is defective.

Claim 12

A memory test circuit capable of testing at least one random access memory circuit, that at least one random access memory circuit being adapted to be embedded on a chip and having address lines, read/write control lines, and separated data input and data output lines, the memory test circuit comprising: (a) a finite state machine means adapted to sequence through a series of states for testing the at least one memory circuit; (b) a counter means, the counter means being connected to the finite state machine means and having a series of output lines equal in number to the number of address lines on the at least one random access memory circuit; (c) a timing generator means, the timing generator means being connected to the finite state machine means and having series of output lines equal in number to the number of read/write control lines on the at least one random access memory circuit; (d) a series of two-input first multiplexer units adapted to be embedded on the chip, the number of first multiplexer units being equal to the total number of data input lines on the at least one memory circuit, those input lines each being associated with a respective one of a series of consecutive bit positions together representing a row addressed in the at least one memory circuit, the output line of each first multiplexer unit being adapted to be connected to a respective one of the data input lines on the at least one memory circuit, a first input line on each first multiplexer unit with the exception of that first multiplexer unit which is associated with the first position being adapted to be connected to the data output line of the consecutive bit position on the at least one memory circuit, the first input line on that first multiplexer unit which is associated with the first bit position being adapted to be connected to a data output port on the finite state machine means, the data output line at the final bit position of the at least one memory circuit being adapted to be connected to a data input port on the finite state machine means, the second input line on each first multiplexer unit being adapted to be connected to a respective one of the lines of a data bus on the chip for sending parallel data to the at least one memory circuit during non-test operation, the data output lines being adapted to be connected to a respective one of the lines of the data bus for receiving parallel data from the at least one memory circuit during non-test operation, the finite state machine means being adapted to be connected to a testing control line on the series of first multiplexer units for selecting whether the data input lines on the at least one memory circuit are connected to either all of the first input lines or all of the second input lines on the first multiplexer units; (e) a series of two-input second multiplexer units adapted to be embedded on the chip, the number of second multiplexer units being equal to the total number of address lines on the at least one memory circuit, the output line of each second multiplexer unit being adapted to be connected to a respective one of those address lines, a first input line of each second multiplexer unit being adapted to be connected to the counter means, a second input line of each second multiplexer unit being adapted to be connected to a respective one of the address lines on the chip for providing address signals to the at least one memory circuit during non-test operation, the testing control line being adapted to be connected to the series of second multiplexer units for selecting whether the address lines of the at least one memory circuit are connected to either all of the first input lines or all of the second input lines on the second multiplexer units; and, (f) a series of two-input third multiplexer units adapted to be embedded on the chip, the number of third multiplexer units being equal to the total number of read/write control lines on the at least one memory circuit, the output line of each third multiplexer unit being adapted to be connected to a respective one of those read/write control lines, a first input line of each third multiplexer unit being adapted to be connected to the timing generator means, a second input line of each third multiplexer unit being adapted to be connected to a respective one of the read/write control lines on the chip for providing read/write control signals to the at least one memory circuit during non-test operation, the testing control line being adapted to be connected to the series of third multiplexer units for selecting whether the read/write control lines of the at least one memory circuit are connected to either all of the first input lines or all of the second input lines on the third multiplexer units; whereby, for purposes of testing the at least one memory circuit, the finite state machine means actuates the testing control line such that the first input lines of the first, second and third multiplexer units are interfaced to the at least one memory circuit, the finite state machine means during such actuation applying each of the possible addresses to the at least one memory circuit and during the application of each address repeatedly performing the steps of applying a test bit to the first input of the first multiplexer unit at the first bit position of the at least one memory circuit, performing a read operation, and performing a write operation, the three steps being repeated at each address a number of times sufficient for the finite state machine means to determine from the test bits received on the data input port whether the at least one memory circuit is defective.