Memory devices

Claim 2

A memory device comprising a semiconductor substrate having a major surface, a plurality of memory cells (11) arranged on said major surface in a matrix configuration and composed of flip-flop circuits for data storage, a plurality of pairs of bit lines (12, 13) formed on said major surface and coupled to each column of the memory cells (11) for handling complementary read-out data or write data, a plurality of word lines (Xi etc) formed on said major surface, one for each row of the memory cells (11), for selecting rows of the memory cells, a sense amplifier (3) arranged on said major surface between each pair of bit lines (12, 13) for amplifying the voltage across each pair of bit lines, equalising means (21) formed on said major surface and operative transiently prior to selection of a memory cell (11) by a word line (Xi etc) to equalise an associated pair of the bit lines (12, 13), equalising control means (8) formed on said major surface for setting the operating time interval of the equalising means (21), first signal generating means (4, 6) formed on said major surface and responsive to address signals supplied for selection of the bit lines (12, 13) and the word lines (Xi etc) to generate a signal for actuating the equalising control means (8), and second signal generating means (7) formed on said major surface and operative to detect a transition from writing to readout and to actuate the equalising control means (8) at the time said transition is detected.

Claim 3

A memory device comprising a semiconductor substrate having a major surface, a plurality of memory cells (11) arranged on said major surface in a matrix configuration and composed of flip-flop circuits for data storage, a plurality of pairs of bit lines (12, 13) formed on said major surface and coupled to each column of the memory cells (11) for handling complementary read-out data or write data, a plurality of word lines (Xi etc) formed on said major surface, one for each row of the memory cells (11), for selecting rows of the memory cells, a plurality of pairs of common data lines (14, 15) formed on said major surface and connected in common to a specified number of bit line pairs (12, 13) for handling complementary read-out data or write data, a sense amplifier (3) connected on said major surface between each pair of common data lines (14, 15) for amplifying the voltage across each pair of the common data lines, common data line equalising means (23) formed on said major surface and operative transiently prior to memory cell selection by a word line (Xi etc) to equalise a pair of the common data lines (14, 15), equalising control means (8, 9) formed on said major surface for setting the operating time interval for the equalising means (23), first signal generating means (4, 6) formed on said major surface and responsive to an address signal supplied for selection of the word lines (Xi etc) and the bit lines (12, 13) to generate a signal for actuating the equalising control means (8, 9), and second signal generating means (7) formed on said major surface and operative to detect a transition from writing to read-out and to actuate the equalising control means (9) at the time said transition is detected.

Claim 4

A memory device comprising a semiconductor substrate having a major surface, a plurality of memory cells (11) arranged on said major surface in a matrix configuration and composed of flip-flop circuits for data storage, a plurality of pairs of bit lines (12, 13) formed on said major surface and coupled to each column of the memory cells (11) for handling complementary read-out data or write data, a plurality of word lines (Xi etc) formed on said major surface, one for each row of the memory cells (11), for selecting rows of the memory cells, a plurality of pairs of common data lines (14, 15) formed on said major surface and connected in common to a specified number of bit line pairs (12, 13) for handling complementary read-out data or write data, a sense amplifier (3) connected on said major surface between each pair of common data lines (14, 15) for amplifying the voltage across each pair of the common data lines, common data line equalising means (23) formed on said major surface and operative transiently prior to memory cell selection by a word line (Xi etc) to equalise a pair of the common data lines (14, 15), equalising control means (8, 9) formed on said major surface for setting the operating time interval for the equalising means (23), first signal generating means (4, 6) formed on said major surface and responsive to an address signal supplied for selection of the word lines (Xi etc) and the bit lines (12, 13) to generate a signal for actuating the equalising control means (8, 9), and second signal generating means (7) formed on said major surface and operative to detect a transition from writing to read-out and to actuate the equalising control means (9) at the time said transition is detected.

Claim 5

A memory device according to claim 2, comprising bit line equalising means (21) formed on said major surface and operative transiently prior to memory cell selection by a word line (Xi etc) to equalise a pair of the bit lines (12, 13), the equalising control means (8, 9) being operative to control the bit line equalising means (21) and the common data line equalising means (23).

Claim 6

A memory device comprising a semiconductor substrate having a major surface, a plurality of memory cells (11) arranged on said major surface in a matrix configuration and composed of flip-flop circuits for data storage, a plurality of pairs of bit lines (12, 13) formed on said major surface and coupled to each column of the memory cells for handling complementary read-out data or write data, a plurality of word lines (Xi etc) formed on said major surface, one for each row of the memory cells (11), for selecting rows of the memory cells, a sense amplifier (3) connected on said major surface between each pair of bit lines (12, 13) for amplifying the voltage across each pair of bit lines, precharging means (22) formed on said major surface and operative transiently prior to memory cell selection by a word line (Xi etc) to precharge each bit line (12, 13) to prevent destruction of data in each memory cell, precharging control means (8) formed on said major surface for controlling the operating time interval of the precharging means (22), first signal generating means (4, 6) formed on said major surface and responsive to address signals supplied for selection of the bit lines (12, 13) to generate a signal for actuating the precharging control means (8), and second signal generating means (7) formed on said major surface and operative to detect a transition from writing to read-out and to actuate the precharging control means (8) at the time said transition is selected. 5. A memory device according to claim 4, comprising equalising means (21) formed on said major surface and operative transiently prior to memory cell selection by a word line (Xi etc) to equalise a pair of bit lines (12, 13), and equalising control means (8) formed on said major surface for setting the operating time interval of the equalising means (21), both the equalising control means (8) and the precharging control means (8) being arranged to be actuated by signals from each of the first signal generating means (4, 6) and the second signal generating means (7).

Claim 7

A memory device comprising a semiconductor substrate having a major surface, a plurality of memory cells (11) arranged on said major surface in a matrix configuration and composed of flip-flop circuits for data storage, a plurality of pairs of bit lines (12, 13) formed on said major surface and coupled to each column of the memory cells (11) for handling complementary read-out data or write data, a plurality of word lines (Xi etc) formed on the major surface, one for each row of the memory cells (11), for selecting rows of the memory cells, a plurality of pairs of common data lines (14, 15) formed on said major surface and connected in common to a specified number of pairs of bit lines (12, 13) for handling complementary read-out data or write data, a sense amplifier (3) connected to each pair of common data lines (14, 15) on said major surface for amplifying the voltage across each pair of the common data lines, common data line precharging means (24) formed on said major surface and operative transiently prior to selection of a memory cell (11) by a word line (Xi etc) to precharge an associated pair of the common data lines (14, 15), precharging control means (8, 9) formed on said major surface for setting the operating time interval of the precharging means (24), first signal generating means (4, 6) formed on said major surface and responsive to address signals supplied for selection of the bit lines (12, 13) to generate a signal for actuating the precharging control means (8, 9), and second signal generating means (7) formed on said major surface and operative to detect a transition from writing to read-out and to actuate the precharging control means (9) at the time said transition is detected.

Claim 8

A memory device comprising a semiconductor substrate having a major surface, a plurality of memory cells (11) arranged on said major surface in a matrix configuration and composed of flip-flop circuits for data storage, a plurality of pairs of bit lines (12, 13) formed on said major surface and coupled to each column of the memory cells (11) for handling complementary read-out data or write data, a plurality of word lines (Xi etc) formed on the major surface, one for each row of the memory cells (11), for selecting rows of the memory cells, a plurality of pairs of common data lines (14, 15) formed on said major surface and connected in common to a specified number of pairs of bit lines (12, 13) for handling complementary read-out data or write data, a sense amplifier (3) connected to each pair of common data lines (14, 15) on said major surface for amplifying the voltage across each pair of the common data lines, common data line precharging means (24) formed on said major surface and operative transiently prior to selection of a memory cell (11) by a word line (Xi etc) to precharge an associated pair of the common data lines (14, 15), precharging control means (8, 9) formed on said major surface for setting the operating time interval of the precharging means (24), first signal generating means (4, 6) formed on said major surface and responsive to address signals supplied for selection of the bit lines (12, 13) to generate a signal for actuating the precharging control means (8, 9), and second signal generating means (7) formed on said major surface and operative to detect a transition from writing to read-out and to actuate the precharging control means (9) at the time said transition is detected.

Claim 9

A memory device according to claim 6, comprising bit line precharging means(22) formed on said major surface and operative transiently prior to memory cell selection by a word line (Xi etc) to precharge a pair of the bit lines (12, 13) the precharging control means (8, 9) being operative to control the bit line precharging means (22) and the common data line precharging means (24).

Claim 10

A memory device according to claim 7, comprising equalising means (23) operative transiently prior to memory cell selection by a word line (Xi etc) to equalise each of a pair of the common data lines (14, 15), equalising means (21) operative transiently prior to selection of a memory cell (11) by a word line (Xi etc) to equalise each of a pair of the bit lines (12, 13), and equalising control means (8, 9) formed on said major surface for controlling each of the equalising means (23, 21), both the equalising control means (8, 9) and the precharging control means (8, 9) being arranged to be controlled by a signal from each of the first signal generating means (4, 6) and the second signal generating means (7).

Claim 11

A memory device according to claim 6, comprising equalising means (23) formed on said major surface and operative transiently prior to memory cell selection by a word line (Xi etc) to equalise a pair of the common data lines (14, 15), and equalising control means (8, 9) formed on said major surface for setting the operating time interval for the equalising means (23), both the equalising control means (8, 9) and the precharging control means (8, 9) being arranged to ' be actuated by a signal from each of the first signal generating means (4, 6) and the second signal generating means (7).

Claim 12

A memory device according to any one of the preceding claims, wherein the second signal generating means (7) is operative to detect a transition from writing to read-out on the basis of a write enable signal.

Claim 13

A memory device comprising a semiconductor substrate having a major surface, a plurality of memory cells (11) arranged on said major surface in a matrix configuration for data storage, a plurality of pairs of bit lines (12, 13) formed on said major surface and coupled to each column of the memory cells (11) for handling complementary read-out data or write data, a plurality of word lines (Xi etc) formed on said major surface, one for each row of the memory cells (11), for selecting rows of the memory cells, a sense amplifier (3) arranged on said major surface between each pair of bit lines (12, 13) for amplifying the voltage across each pair of bit lines to produce an output signal, and an output circuit (5) for amplifying the output signal from said sense amplifier (3), the output circuit (5) including an output terminal (55;75) for outputting the amplified output signal from the sense amplifier (3), output means (61, 62; 81, 82) for driving said output terminal (55; 75) to a first level or a second level, level detection means (51, 52; 71, 72) for detecting the level at said output terminal (55; 75), and precharging means (53, 54; 73, 74) responsive to a signal from said level detection means (51, 52; 71, 72) to precharge the level at said output terminal to a third level between the first level and the second level.

Claim 14

A memory device comprising a semiconductor substrate having a major surface, a plurality of memory cells (11) arranged on said major surface in a matrix configuration for data storage, a plurality of pairs of bit lines (12, 13) formed on said major surface and coupled to each column of the memory cells (11) for handling complementary read-out data or write data, a plurality of word lines (Xi etc) formed on said major surface, one for each row of the memory cells (11), for selecting rows of the memory cells, a sense amplifier (3) arranged on said major surface between each pair of bit lines (12, 13) for amplifying the voltage across each pair of bit lines to produce an output signal, and an output circuit (5) for amplifying the output signal from said sense amplifier (3), the output circuit (5) including an output terminal (55;75) for outputting the amplified output signal from the sense amplifier (3), output means (61, 62; 81, 82) for driving said output terminal (55; 75) to a first level or a second level, level detection means (51, 52; 71, 72) for detecting the level at said output terminal (55; 75), and precharging means (53, 54; 73, 74) responsive to a signal from said level detection means (51, 52; 71, 72) to precharge the level at said output terminal to a third level between the first level and the second level.

Claim 15

A memory device according to claim 11, wherein the level detection means (51, 52; 71, 72) is operative transiently in response to an equalising signal generated in response to address transitions.

Claim 16

A memory device according to claim 11 or claim 12, wherein the precharging means (53, 54) includes an MOS transistor (53, 54) having a drain connected at least to said output terminal (55) and having a gate connected to an output of the level detection means (51, 52).

Claim 17

A memory device according to claim 11 or claim 12, wherein the precharging means (73, 74) comprises an MOS transistor (73, 74) having a source connected at least to said output terminal (75) and having a gate connected to an output of the level detection means (71, 72).

Claim 18

A memory device according to claim 11, wherein said third level is an output decision level.

Claim 19

A memory device according to claim 11, wherein the first level is a source voltage, the second level is a ground voltage, and the third level is a TTL compatible output decision level.