Patent EP0382360A2 successfully refreshed from Google Patents.
EP0382360A2
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EP
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Event qualified testing architecture for integrated circuits
Assignee: Texas Instruments Inc
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Filing: 1990-01-22
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Granted: —
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Expires: 2010-01-22
Abstract
Abstract A boundary test architecture for use in an integrated circuit (10) comprises input and output test registers (12, 22) having functions controlled by a event qualifying module (EQM) (30). The EQM (30) receives a signal from the output test register (22) indicating that a matching condition has been met. In response to a matching condition, EQM (30) may control the input and output test on the incoming and outgoing data. During testing, tests on the incoming and outgoing data. During testing the internal logic (20) may continue to operate at-speed, thereby allowing the test circuitry to detect faults which would not otherwise be discoverable. A memory buffer (64) may be included to store a plurality of input data for test data.
Inventors
- 👤 Lee D. Whetsel
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 12:19
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318555; H; H10; H10P; H10P74/00; G01R31/318558; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/267; G06F2201/00; G06F2201/86
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
73 words
A test architecture for use in conjunction with an integrated circuit comprising: input circuitry for receiving incoming data; output circuitry for outputting data from the integrated circuit; logic circuitry connected between said input and output circuitry for performing a desired function on said incoming data; and test circuitry connected to said input and output circuitry for storing data in response to a predetermined condition while the integrated circuit is in a functioning mode.
Claim 2
Dependent Claim
73 words
A test architecture for use in conjunction with an integrated circuit comprising: input circuitry for receiving incoming data; output circuitry for outputting data from the integrated circuit; logic circuitry connected between said input and output circuitry for performing a desired function on said incoming data; and test circuitry connected to said input and output circuitry for storing data in response to a predetermined condition while the integrated circuit is in a functioning mode.
Claim 3
Dependent Claim
47 words
The test architecture of Claim 1 wherein said test circuitry comprises: input test circuitry connected to said input circuitry; output test circuitry connected to said output circuitry; and event qualification circuitry connected to said input and output test circuitry to indicate when said predetermined condition has occurred.
Claim 4
Dependent Claim
42 words
The test architecture of Claim 1 and further comprising scan path circuitry for transferring said stored data from the integrated circuit separate from said output circuitry such that the normal data flow through said output circuitry is not interrupted by said transfer.
Claim 5
Dependent Claim
78 words
A boundary test architecture for use in an integrated circuit comprising: input circuitry for receiving incoming data; output circuitry for outputting data from the integrated circuit; logic circuitry connected between said input and output circuitry for performing a desired function on said incoming data; and test circuitry connected to said output circuitry for inserting test data to be output from the integrated circuit in response to a predetermined condition while the integrated circuit is in a functioning mode.
Claim 6
Dependent Claim
78 words
A boundary test architecture for use in an integrated circuit comprising: input circuitry for receiving incoming data; output circuitry for outputting data from the integrated circuit; logic circuitry connected between said input and output circuitry for performing a desired function on said incoming data; and test circuitry connected to said output circuitry for inserting test data to be output from the integrated circuit in response to a predetermined condition while the integrated circuit is in a functioning mode.
Claim 7
Dependent Claim
47 words
The testing architecture of Claim 4 wherein said test circuitry comprises: input test circuitry connected to said input circuitry; output test circuitry connected to said output circuitry; and event qualification circuitry connected to said input and output test circuitry to indicate when said predetermined condition has occurred.
Claim 8
Dependent Claim
41 words
The test architecture of Claim 4 and further comprising scan path circuitry separate from said output circuitry such that said output test circuitry can be loaded with said data to be inserted without interrupting normal data flow through said output circuit.
Claim 9
Independent Claim
56 words
A method of testing integrated circuits comprising the steps of: receiving incoming data; performing a desired function on said incoming data; outputting data on which said function has been performed; detecting the occurrence of a predetermined condition; and processing input data in response to said predetermined condition while the integrated circuit is in the functioning mode.
Claim 10
Independent Claim
56 words
A method of testing integrated circuits comprising the steps of: receiving incoming data; performing a desired function on said incoming data; outputting data on which said function has been performed; detecting the occurrence of a predetermined condition; and processing input data in response to said predetermined condition while the integrated circuit is in the functioning mode.
Claim 11
Independent Claim
45 words
A method of testing integrated circuits comprising the steps of: receiving incoming data; performing a desired function on said incoming data; detecting the occurrence of a predetermined condition; and outputting test data from the integrated circuit in response to the detection of the predetermined condition.
Claim 12
Independent Claim
45 words
A method of testing integrated circuits comprising the steps of: receiving incoming data; performing a desired function on said incoming data; detecting the occurrence of a predetermined condition; and outputting test data from the integrated circuit in response to the detection of the predetermined condition.
Claim 13
Independent Claim
49 words
A method of testing integrated circuits comprising the steps of: detecting a first signal to determine whether a test operation is desired; detecting a second signal in response to said first signal, said second signal indicative of a desired protocol; and performing a test operation using said desired protocol.
Claim 14
Independent Claim
49 words
A method of testing integrated circuits comprising the steps of: detecting a first signal to determine whether a test operation is desired; detecting a second signal in response to said first signal, said second signal indicative of a desired protocol; and performing a test operation using said desired protocol.
Claim 15
Dependent Claim
51 words
Apparatus for testing integrated circuits comprising: circuitry for detecting a first signal to determine whether a test operation is desired; circuitry for detecting a second signal in response to said first signal, said second signal indicative of a desired protocol; and circuitry for performing a test operation using said desired protocol.
Claim 16
Dependent Claim
51 words
Apparatus for testing integrated circuits comprising: circuitry for detecting a first signal to determine whether a test operation is desired; circuitry for detecting a second signal in response to said first signal, said second signal indicative of a desired protocol; and circuitry for performing a test operation using said desired protocol.
References Cited (Backward Citations)
US5495487A
Cited
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