Patent EP0382184A2 successfully refreshed from Google Patents.
EP0382184A2
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Circuit for testability
Assignee: Toshiba Corp
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Filing: 1990-02-07
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Granted: —
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Expires: 2010-02-07
Abstract
Abstract Disclosed is a circuit for testability to be provided in a logic circuit comprising a plurality of functional groups which are respectively composed of a plurality of register groups (100 to 107) respectively comprising a plurality of resisters having the same functions. The circuit for testability is characterized by composition in which each the register group (100 to 107) is corresponding to each scan path (SP100 to SP107), and each the scan path (SP100 to SP107) is selected by an address decoder (118), further each the register group (100 to 107) carries out input and output of data to bus lines (IB0 to IB7) through the corresponding scan path (SP100 to SP107), whereby register groups can be divided so as to separate tests on an internal logic circuit of the functional blocks (22, 24) and tests on a logic circuit related to I/O signals of the functional blocks (22, 24). Further disclosed is another circuit for testability characterized by composition in which scan paths respectively corresponding to register groups (100 to 107) which are inputted test data and those outputted test data in functional blocks (22, 24) as objects in the tests are connected to the same bus lines, whereby the number of the bus lines to be required can be reduced.
Inventors
- 👤 Toshiyuki Yaguchi
- 👤 Koichi Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 12:57
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
189 words
A circuit for testability to be provided in a logic circuit composed of a plurality of functional blocks, comprising; a plurality of register groups (100 to 107) obtained by division of a plurality of registers included in the functional blocks (22, 24); scan paths (SP100 to SP107) for scanning the register groups (100 to 107) so as to carry out input and output of storage contents of the register groups (100 to 107) respectively corresponding thereto; and control means (118) for designating addresses of the scan paths (SP100 to SP107) and controlling input and output of test signals for the register groups (100 to 107) respectively corresponding to the scan paths (SP100 to SP107); and one portion of a plurality of the register groups (100 to 107) included in one of the functional blocks (22, 24) being composed of only registers related to input and output of the others of the functional blocks (22, 24), and the other portion of the register groups (100 to 107) being composed of only registers other than those related to the input and output of the others of the functional blocks (22, 24).
Claim 2
Dependent Claim
189 words
A circuit for testability to be provided in a logic circuit composed of a plurality of functional blocks, comprising; a plurality of register groups (100 to 107) obtained by division of a plurality of registers included in the functional blocks (22, 24); scan paths (SP100 to SP107) for scanning the register groups (100 to 107) so as to carry out input and output of storage contents of the register groups (100 to 107) respectively corresponding thereto; and control means (118) for designating addresses of the scan paths (SP100 to SP107) and controlling input and output of test signals for the register groups (100 to 107) respectively corresponding to the scan paths (SP100 to SP107); and one portion of a plurality of the register groups (100 to 107) included in one of the functional blocks (22, 24) being composed of only registers related to input and output of the others of the functional blocks (22, 24), and the other portion of the register groups (100 to 107) being composed of only registers other than those related to the input and output of the others of the functional blocks (22, 24).
Claim 3
Dependent Claim
44 words
A circuit for testability according to claim 1, wherein each of the scan paths (SP100 to SP107) is connected to a common bus (108) of the logic circuit and carries out the input and output of the test data through the common bus (108).
Claim 4
Dependent Claim
60 words
A circuit for testability according to claim 2, wherein switch means (110 to 117) is provided to each of the scan paths (SP100 to SP107), each the switch means (110 to 107) is connected to the controlling means (118), and selection of each the scan paths (SP100 to SP107) is carried out by each the switch means (110 to 107).
Claim 5
Dependent Claim
41 words
A circuit for testability according to claim 2, wherein both of the register groups (100 to 107) related to the input and those related to the output are connected to the same signal lines (IB′0, IB′1) in the common bus (208).
Claim 6
Dependent Claim
37 words
A circuit for testability according to claim 2, wherein a plurality of the register groups (100 to 107) included in the functional blocks (22, 24) are respectively connected to different signal lines of the common bus (108).
Claim 7
Dependent Claim
169 words
A circuit for testability to be provided in a logic circuit having a plurality of functional blocks (22, 24) comprising a circuit portion related to input and output and another circuit portion related to functions other than the input and output, comprising: a plurality of register groups (100 to 107) composed a plurality of registers included in the functional blocks (22, 24) respectively; first scan paths for efffecting input and output of storage contents of one portion of the register groups belonging to the circuit portion related to the input and output; second scan paths for effecting input and output of storage contents of the other portion of the register groups belonging to the circuit portion related to the functions other than the input and output; and control means (118) for controlling operation of the first and the second scan paths so as to carry out input and output of test data through the scan paths; and the first and the second scan paths are respectively and independently provided.
Claim 8
Dependent Claim
169 words
A circuit for testability to be provided in a logic circuit having a plurality of functional blocks (22, 24) comprising a circuit portion related to input and output and another circuit portion related to functions other than the input and output, comprising: a plurality of register groups (100 to 107) composed a plurality of registers included in the functional blocks (22, 24) respectively; first scan paths for efffecting input and output of storage contents of one portion of the register groups belonging to the circuit portion related to the input and output; second scan paths for effecting input and output of storage contents of the other portion of the register groups belonging to the circuit portion related to the functions other than the input and output; and control means (118) for controlling operation of the first and the second scan paths so as to carry out input and output of test data through the scan paths; and the first and the second scan paths are respectively and independently provided.
Claim 9
Dependent Claim
26 words
A circuit for testability according to claim 6, wherein the first scan paths further comprise scan paths related to input and those related to output respectively.
Claim 10
Dependent Claim
19 words
A circuit for testability according to claim 6, wherein the register groups (100 to 107) comprise shift registers respectively.
References Cited (Backward Citations)
No citation records indexed.
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