Apparatus and method for changing frequencies

Claim 2

Frequency control apparatus for providing a selected one of two frequencies to a microprocessor characterized by: first frequency generating means (X2) capable of generating a signal having a first frequency; second frequency generating means (X1) capable of generating a signal having a second frequency; a microprocessor (30) to which signals of said first frequency or said second frequency are selectively applied; logic circuit means (46, 48, 50) adapted to selectively gate a signal from either said first frequency generating means (X2) or said second frequency generating means (X1) to said microprocessor (30); flip-flop means (52) adapted to control said logic circuit means (46, 48, 50) and having a data input coupled to an output of said microprocessor (30); address decoder means (40) controlled by said microprocessor (30) and coupled to a clock input of said flip-flop means (52); memory means (36) coupled to said microprocessor (30) to provide data to said microprocessor (30) for control thereof; and reset means (80, 84) controlled by said address decoder means (40) and coupled to said microprocessor (30) for resetting said microprocessor (30).

Claim 3

Frequency control apparatus according to claim 1, characterized in that said logic circuit means (46, 48, 50) comprises: a first NOR gate (46) having one input coupled to said first frequency generating means (X2) and a second input coupled to a first output of said flip-flop means (52); a second NOR gate (48) having one input coupled to said second frequency generating means (X1) and a second input coupled to a second output of said flip-flop means (52); and a third NOR gate (50) having first and second inputs coupled to the outputs of said first and second NOR gates (46, 48) and having an output coupled to said microprocessor (30).

Claim 4

Frequency control apparatus according to claim 1, characterized in that said reset means includes a coupled NOR (80) gate and a monostable multivibrator (84).

Claim 5

Frequency control apparatus according to claim 1, characterized by an address latch (34) which is coupled to certain of the outputs of the microprocessor (30) and to certain of the inputs of the memory means (36) and which provides a portion of the address when the microprocessor (30) addresses the memory (36).

Claim 6

Frequency control apparatus according to claim 1, characterized by selection means (18) adapted to select one of the two frequencies.

Claim 7

Frequency control apparatus according to claim 1, characterized in that byte patterns of data representing the first and second frequency generating means are stored in said memory means (36), and in that one of said byte patterns can be stored in a random access memory of said microprocessor (30) to enable said microprocessor (30) to select the corresponding frequency.

Claim 8

Frequency control apparatus according to claim 1, characterized in that frequency selection is accomplished by the microprocessor (30) by comparing the byte pattern stored in the random access memory of the microprocessor (30) with at least one of the byte patterns stored in the memory means (36).

Claim 9

A process for providing a selected one of two different frequencies from two frequency generating means through logic means (46, 48, 50) to a microprocessor (30) having memory means, characterized by the following steps: (a) determining whether a data pattern in the microprocessor memory is identical to a first reference pattern associated with a first of two frequencies; (b) if said patterns are identical, controlling said logic means (46, 48, 50) to cause a first of the two frequencies to be provided to the microprocessor (30) from a first frequency generating means (X2); (c) if said patterns are not identical, determining whether the data pattern in the microprocessor memory is identical to a second reference pattern associated with a second of the two frequencies; (d) if said data pattern and said second reference pattern are identical, controlling said logic means (46, 48, 50) to cause a second of the two frequencies to be provided to the microprocessor (30) from a second frequency generating means (X1); (e) if said data pattern and said second reference pattern are not identical, determining which of the two frequencies is required; (f) writing a reference pattern associated with the selected one of the two frequencies into the microprocessor memory means; (g) resetting the microprocessor (30); (h) making a further determination as to whether the data pattern which has been written into the microprocessor memory is identical to said first reference pattern; and (i) repeating conditional steps (b), (c) and (d) to cause the desired frequency to be provided to the microprocessor until the desired frequency is changed.

Claim 10

A process for providing a selected one of two different frequencies from two frequency generating means through logic means (46, 48, 50) to a microprocessor (30) having memory means, characterized by the following steps: (a) determining whether a data pattern in the microprocessor memory is identical to a first reference pattern associated with a first of two frequencies; (b) if said patterns are identical, controlling said logic means (46, 48, 50) to cause a first of the two frequencies to be provided to the microprocessor (30) from a first frequency generating means (X2); (c) if said patterns are not identical, determining whether the data pattern in the microprocessor memory is identical to a second reference pattern associated with a second of the two frequencies; (d) if said data pattern and said second reference pattern are identical, controlling said logic means (46, 48, 50) to cause a second of the two frequencies to be provided to the microprocessor (30) from a second frequency generating means (X1); (e) if said data pattern and said second reference pattern are not identical, determining which of the two frequencies is required; (f) writing a reference pattern associated with the selected one of the two frequencies into the microprocessor memory means; (g) resetting the microprocessor (30); (h) making a further determination as to whether the data pattern which has been written into the microprocessor memory is identical to said first reference pattern; and (i) repeating conditional steps (b), (c) and (d) to cause the desired frequency to be provided to the microprocessor until the desired frequency is changed.

Claim 11

A process according to claim 8, characterized in that said first and second reference patterns are stored in a read-only memory (36).

Claim 12

A process according to claim 8, characterized in that said logic means (46, 48, 50) is controlled in steps (b) and (d) by said microprocessor (30) performing an external read operation which causes a signal to be sent to said logic means (46, 48, 50).