Patent EP0381371A2 successfully refreshed from Google Patents.
EP0381371A2
Expired / Lapsed
EP
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A burst mode digital data receiver
Assignee: AT&T Inc
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Filing: 1990-01-25
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Granted: —
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Expires: 2010-01-25
Abstract
Abstract A burst mode digital data receiver automatically adjusts its logic reference voltage to be equal to one-half of the sum of the minimum and maximum excursions of a received data signal. The receiver includes a differential amplifier circuit which has a first input for receiving the data signal and a second input connected to a voltage reference circuit. The voltage reference circuit is responsive to an output signal from the amplifier circuit to produce the required logic reference voltage at the second input to the amplifier circuit by generating a feedback signal which causes the amplifier circuit to have a first gain value during the absence of the data signal and while the data signal is less than its peak amplitude and a second gain value approximately twice the first gain value for a predetermined time after the peak amplitude of the data signal is reached.
Inventors
- 👤 Yusuke Ota
- 👤 Robert Gerald Swartz
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:06
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04B; H04B10/00; H04B10/60; H04B10/66; H04B10/69; H04B10/693; H04B10/6933
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
114 words
A digital data receiver (500) CHARACTERIZED BY a DC-coupled differential amplifier circuit (501) having a first input for receiving a digital data input signal, a second input for receiving a reference signal (V REF ), and a data output, and means (502) responsive to said data output for generating said reference signal in such a way that said amplifier circuit has a first gain value during the absence of said data input signal and while the data input signal is less than its peak amplitude, and has a second gain value approximately equal to twice the first gain value for a predetermined time after the peak amplitude of the data input signal is reached.
Claim 2
Dependent Claim
114 words
A digital data receiver (500) CHARACTERIZED BY a DC-coupled differential amplifier circuit (501) having a first input for receiving a digital data input signal, a second input for receiving a reference signal (V REF ), and a data output, and means (502) responsive to said data output for generating said reference signal in such a way that said amplifier circuit has a first gain value during the absence of said data input signal and while the data input signal is less than its peak amplitude, and has a second gain value approximately equal to twice the first gain value for a predetermined time after the peak amplitude of the data input signal is reached.
Claim 3
Dependent Claim
29 words
A receiver as claimed in claim 1 wherein said responsive means is connected in a feedback loop between said data output and said second input of said amplifier circuit.
Claim 4
Dependent Claim
16 words
A receiver as claimed in claim 2 wherein said responsive means includes a peak detector circuit.
Claim 5
Dependent Claim
33 words
A receiver as claimed in claim 3 wherein said amplifier circuit and said peak detector circuit each include an amplifier means (A1, A2) having operating characteristics which are substantially matched to each other.
Claim 6
Dependent Claim
26 words
A receiver as claimed in claim 3 or 4 wherein said amplifier circuit and said peak detector circuit are implemented as part of an integrated circuit.
Claim 7
Dependent Claim
58 words
A receiver as claimed in claim 3, 4 or 5, wherein said amplifier circuit has a first feedback loop (Z T ) to regulate the magnitude of the input current to voltage output characteristic of said amplifier circuit, and said peak detector circuit has a first feedback loop (504) to control the gain of the peak detector circuit.
Claim 8
Dependent Claim
43 words
A receiver as claimed in claim 3, 4 or 5 wherein said peak detector circuit includes means (C PD ) for storing the peak amplitude of said data input signal, and amplifier means for controlling the discharge rate of said means for storing.
Claim 9
Dependent Claim
35 words
A receiver as claimed in claim 7 wherein said means for storing is connected in said feedback loop and is connected in another feedback loop (504) which controls the gain of said peak detector circuit.
Claim 10
Dependent Claim
49 words
A receiver as claimed in any one of claims 2 to 8 wherein the first-mentioned feedback loop includes a parallel resistor and capacitor network (C1,R3) connected in series to said second input of said amplifier circuit to cancel an impedance pole at the second input of said amplifier circuit.
Claim 11
Dependent Claim
78 words
A receiver as claimed in any one of claims 2 to 9 wherein said responsive means and said amplifier circuit are adapted to operate at substantially the same maximum data rate, the first-mentioned feedback loop is stable at the maximum data rate of said amplifier circuit, and the resulting voltage on said second input is substantially equal to the dc centre of the input signal within a single bit period following the beginning of a received data burst.
Claim 12
Dependent Claim
32 words
A receiver as claimed in any preceding claim wherein said amplifier circuit includes means (R15,R20) for selecting a dc offset current between said first and said second inputs of the amplifier circuit.
Claim 13
Dependent Claim
130 words
A burst mode digital data receiver (500) CHARACTERIZED BY a DC-coupled differential amplifier circuit (501) having a first input for receiving a burst mode digital data input signal, a second input connected to a voltage reference circuit (502), and a data output, said voltage reference circuit being connected in a feedback loop between said data output and said second input for generating a reference dc voltage (V REF ) substantially equal to the dc centre of the input signal within a single bit period following the beginning of a received burst mode digital data input signal, said voltage reference circuit and said amplifier circuit having substantially the same maximum data transmission rate operating characteristics, and said feedback loop being stable at the maximum data transmission rate of said amplifier circuit.
Claim 14
Dependent Claim
130 words
A burst mode digital data receiver (500) CHARACTERIZED BY a DC-coupled differential amplifier circuit (501) having a first input for receiving a burst mode digital data input signal, a second input connected to a voltage reference circuit (502), and a data output, said voltage reference circuit being connected in a feedback loop between said data output and said second input for generating a reference dc voltage (V REF ) substantially equal to the dc centre of the input signal within a single bit period following the beginning of a received burst mode digital data input signal, said voltage reference circuit and said amplifier circuit having substantially the same maximum data transmission rate operating characteristics, and said feedback loop being stable at the maximum data transmission rate of said amplifier circuit.
Claim 15
Dependent Claim
140 words
A burst mode digital data receiver (5001 CHARACTERIZED BY a DC-coupled differential input amplifier circuit (501) having a first input for receiving a burst mode digital data input signal and a second input connected to a reference voltage circuit (502), said reference voltage circuit being responsive to an output data signal from said amplifier circuit for generating a dc-voltage approximately equal to one-half of the amplitude of a received data input signal within a predetermined time of the beginning of the data input signal, and said receiver having a first gain value during the absence of said data input signal and while the data input signal is less than its peak amplitude and a second gain value approximately equal to twice the first gain value for a predetermined time after the peak amplitude of the data input signal is reached.
Claim 16
Dependent Claim
140 words
A burst mode digital data receiver (5001 CHARACTERIZED BY a DC-coupled differential input amplifier circuit (501) having a first input for receiving a burst mode digital data input signal and a second input connected to a reference voltage circuit (502), said reference voltage circuit being responsive to an output data signal from said amplifier circuit for generating a dc-voltage approximately equal to one-half of the amplitude of a received data input signal within a predetermined time of the beginning of the data input signal, and said receiver having a first gain value during the absence of said data input signal and while the data input signal is less than its peak amplitude and a second gain value approximately equal to twice the first gain value for a predetermined time after the peak amplitude of the data input signal is reached.
Claim 17
Dependent Claim
124 words
A digital data receiver (500) CHARACTERIZED BY a DC-coupled differential amplifier circuit (501) having a first input for receiving a digital data input signal, a second input connected to a voltage reference circuit (502), and a data output, said voltage reference circuit being connected in a feedback loop between said data output and said second input for generating a feedback signal to said amplifier circuit, resulting in said receiver having a first gain value during the absence of said data input signal and while the data input signal is less than its peak amplitude and having a second gain value approximately equal to two times the first gain value for a predetermined time after the peak amplitude of the data input signal is reached.
Claim 18
Dependent Claim
124 words
A digital data receiver (500) CHARACTERIZED BY a DC-coupled differential amplifier circuit (501) having a first input for receiving a digital data input signal, a second input connected to a voltage reference circuit (502), and a data output, said voltage reference circuit being connected in a feedback loop between said data output and said second input for generating a feedback signal to said amplifier circuit, resulting in said receiver having a first gain value during the absence of said data input signal and while the data input signal is less than its peak amplitude and having a second gain value approximately equal to two times the first gain value for a predetermined time after the peak amplitude of the data input signal is reached.
References Cited (Backward Citations)
No citation records indexed.
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