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EP0380842A2
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Method and apparatus for interfacing a system control unit for a multiprocessor system with the central processing units
Assignee: Digital Equipment Corp
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Filing: 1989-06-27
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Granted: —
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Expires: 2009-06-27
Abstract
Abstract A computer system includes a plurality of central processing units (CPUs), a main memory, and a system control unit (SCU) for controlling the transfer of data between the CPUs and main memory. In addition to main memory, each of the CPUs includes a high-speed cache of selected portions of the main memory. Accordingly, these is an inherent risk that data contained in the caches may be altered while the identical data contained in main memory remains in the unaltered state. This, of course, leads to data inconsistency problems. Thus, in order to avoid data inconsistency, the SCU effects control over all data transfers to ensure that multiple versions of the same data are not maintained in the computer system. Further, memory references can be speeded by accessing the high-speed CPU caches when the desired data exits in the cache of another CPU.
Inventors
- 👤 Scott Arnold
- 👤 Stephen J. Delahunt
- 👤 Michael E. Flynn
- 👤 Ricky C. Hetherington
- 👤 Mohamed Baser-Uddin Ahmed
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 17:23
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/0822
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
211 words
A computer system having a plurality of central processing units, a main memory, a system control unit for controlling the transfer of data between the central processing units and main memory, each of the central processing units having a cache for containing selected portions of the data maintained in the main memory, said system control unit comprising: means for receiving a request for data contained in a selected address of the main memory from one of the central processing units; means for initiating data retrieval from the main memory in response to receiving a data request; means for comparing the requested data address to the addresses of the data contained in each of the central processing unit caches and delivering one of a respective hit and miss signal in response to detecting a match and the absence of a match therebetween; means for aborting the data retrieval initiating means in response to receiving the hit signal; means for retrieving the requested data from the central processing unit cache and delivering the retrieved data to the requesting central processing unit cache in response to receiving a hit signal; and means for delivering the data retrieved from main memory to the requesting central processing unit cache in response to receiving the miss signal.
Claim 2
Dependent Claim
211 words
A computer system having a plurality of central processing units, a main memory, a system control unit for controlling the transfer of data between the central processing units and main memory, each of the central processing units having a cache for containing selected portions of the data maintained in the main memory, said system control unit comprising: means for receiving a request for data contained in a selected address of the main memory from one of the central processing units; means for initiating data retrieval from the main memory in response to receiving a data request; means for comparing the requested data address to the addresses of the data contained in each of the central processing unit caches and delivering one of a respective hit and miss signal in response to detecting a match and the absence of a match therebetween; means for aborting the data retrieval initiating means in response to receiving the hit signal; means for retrieving the requested data from the central processing unit cache and delivering the retrieved data to the requesting central processing unit cache in response to receiving a hit signal; and means for delivering the data retrieved from main memory to the requesting central processing unit cache in response to receiving the miss signal.
Claim 3
Independent Claim
159 words
A method for controlling the transfer of data between central processing units and main memory in a computer system, each of the central processing units having a cache for containing selected portions of the data maintained in the main memory, said method comprising the steps of: receiving a request for data contained in a selected address of the main memory from one of the central processing units; comparing the requested data address to the addresses of the data contained in each of the central processing unit caches and delivering one of a respective hit and miss signal in response to detecting a match and the absence of a match therebetween; retrieving the requested data from the respective central processing unit cache and delivering the retrieved data to the requesting central processing unit in response to the hit signal; and delivering the requested data retrieved from main memory to the requesting central processing unit in response to the miss signal.
Claim 4
Independent Claim
159 words
A method for controlling the transfer of data between central processing units and main memory in a computer system, each of the central processing units having a cache for containing selected portions of the data maintained in the main memory, said method comprising the steps of: receiving a request for data contained in a selected address of the main memory from one of the central processing units; comparing the requested data address to the addresses of the data contained in each of the central processing unit caches and delivering one of a respective hit and miss signal in response to detecting a match and the absence of a match therebetween; retrieving the requested data from the respective central processing unit cache and delivering the retrieved data to the requesting central processing unit in response to the hit signal; and delivering the requested data retrieved from main memory to the requesting central processing unit in response to the miss signal.
Claim 5
Dependent Claim
40 words
The method of claim 2, wherein data retrieval from the main memory is initiated in response to receiving the request for data, and wherein the data retrieval from the main memory is aborted in response to receiving the hit signal.
References Cited (Backward Citations)
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