Patent EP0378426A2 successfully refreshed from Google Patents.
EP0378426A2
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EP
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Data transfer using bus address lines
Assignee: International Business Machines Corp
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Filing: 1990-01-11
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Granted: —
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Expires: 2010-01-11
Abstract
Abstract A computer system is described which can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.
Inventors
- 👤 Ravi Kumar Arimilli
- 👤 Sudhir Dhawan
- 👤 James Otto Nicholson
- 👤 David William Siegel
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 12:17
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
105 words
A system for transferring data in a digital computer, comprising: a bus (10) having address lines, data lines, and control lines; a master subsystem (12) connected to said bus; a slave subsystem (14) connected to said bus; a control line in said bus for communicating a transfer mode signal, wherein data is transferred between said master subsystem and said slave subsystem on the data lines when the transfer mode signal indicates a first mode, and wherein data is transferred between said master subsystem and said slave subsystem on the data lines and on the address lines when the transfer mode signal indicates a second mode.
Claim 2
Independent Claim
105 words
A system for transferring data in a digital computer, comprising: a bus (10) having address lines, data lines, and control lines; a master subsystem (12) connected to said bus; a slave subsystem (14) connected to said bus; a control line in said bus for communicating a transfer mode signal, wherein data is transferred between said master subsystem and said slave subsystem on the data lines when the transfer mode signal indicates a first mode, and wherein data is transferred between said master subsystem and said slave subsystem on the data lines and on the address lines when the transfer mode signal indicates a second mode.
Claim 3
Dependent Claim
30 words
A system as claimed in Claim 1, wherein, prior to transferring data in the second mode, said master subsystem communicates an address on the address lines to said slave subsystem.
Claim 4
Dependent Claim
61 words
A system as claimed in Claim 1 or Claim 2, further comprising: a clock line in said bus for communicating a clock signal; and a high speed clock line in said bus for communicating a high speed clock signal; wherein data is transferred during each cycle of the high speed clock signal when the transfer mode signal indicates the second mode.
Claim 5
Dependent Claim
112 words
A system as claimed in Claim 3, further comprising: a transfer rate line in said bus for communicating a transfer rate signal, wherein the high speed clock signal operates at a rate determined by the transfer rate signal when the transfer mode signal indicates the second mode; and a ready line in said bus for communicating a ready signal under control of said slave subsystem, wherein data is transferred during each cycle of the high speed clock when the ready signal indicates that said slave subsystem is ready to transfer data, and wherein data transfer is suspended when the ready signal indicates that said slave subsystem is not ready to transfer data.
Claim 6
Independent Claim
58 words
A method for transferring data between a master subsystem (12) and a slave subsystem (14) over a computer system bus (10) having address lines and data lines, comprising the steps of: the master subsystem initiating a data transfer; and transferring data between the master subsystem and the slave subsystem on the address lines and on the data lines.
Claim 7
Independent Claim
58 words
A method for transferring data between a master subsystem (12) and a slave subsystem (14) over a computer system bus (10) having address lines and data lines, comprising the steps of: the master subsystem initiating a data transfer; and transferring data between the master subsystem and the slave subsystem on the address lines and on the data lines.
Claim 8
Dependent Claim
62 words
A method as claimed in Claim 5, further comprising the steps of: the master subsystem determining whether the slave subsystem is capable of transferring data on the data lines and on the address lines, and in response to said determination, the master subsystem selecting whether to transfer data on the address lines and the data lines, or on the data lines only.
Claim 9
Dependent Claim
34 words
A method as claimed in Claim 5 or Claim 6, further comprising the step of: before said transferring step, communicating an address from the master subsystem to the slave subsystem on the address lines.
Claim 10
Independent Claim
56 words
A method as claimed in any of Claims 5 to 7, wherein said bus includes means for communicating a normal bus clock signal, further comprising the steps of: generating a high speed transfer clock signal separate and distinct from said normal bus clock signal; and transferring data during each cycle of said high speed transfer clock.
Claim 11
Dependent Claim
34 words
A method as claimed Claim 8, wherein the signal generated in said clock signal generating step has a speed limited by a maximum common transfer rate of said master subsystem and said slave subsystem.
Claim 12
Dependent Claim
61 words
A method as claimed in Claim 8, wherein said slave subsystem further includes means for indicating to the master subsystem whether the slave subsystem is ready to transfer data further comprising the step of: if the slave subsystem indicates that the slave subsystem is not ready to transfer data, suspending data transfer until the slave subsystem is ready to transfer data.
Claim 13
Independent Claim
44 words
A device (12) for transferring data on a computer system bus (10) having address lines and data lines, comprising: means for communicating a starting address to the bus address lines; and means for transferring data on the data lines and on the address lines.
Claim 14
Independent Claim
44 words
A device (12) for transferring data on a computer system bus (10) having address lines and data lines, comprising: means for communicating a starting address to the bus address lines; and means for transferring data on the data lines and on the address lines.
Claim 15
Dependent Claim
59 words
A device as claimed in Claim 11, further comprising: means for generating a normal bus clock signal; means for transferring data during each cycle of the normal bus clock signal means for generating a high speed clock signal separate from said normal bus clock signal; and means for transferring data during each cycle of the high speed clock signal.
Claim 16
Dependent Claim
52 words
A device as claimed in Claim 12, further comprising: means for limiting the speed of the high speed clock signal to a rate limited by a maximum transfer rate of another device connected to the bus; and means for suspending data transfer if the other device is not ready to transfer data.
Claim 17
Independent Claim
44 words
A device (14) for transferring data on a computer system bus (10) having address lines and data lines, comprising: means for reading a starting address from the bus address lines; and means for transferring data on the data lines and on the address lines.
Claim 18
Independent Claim
44 words
A device (14) for transferring data on a computer system bus (10) having address lines and data lines, comprising: means for reading a starting address from the bus address lines; and means for transferring data on the data lines and on the address lines.
Claim 19
Dependent Claim
48 words
A device as claimed in Claim 14, further comprising: means for transferring data during each cycle of a normal bus clock signal on said bus, and means for transferring data during each cycle of a high speed clock signal which is separate from said normal bus clock signal.
Claim 20
Dependent Claim
45 words
A device as claimed in Claim 15, further comprising: means for indicating a maximum data transfer rate for transfers made during high speed clock signal cycles; and means for indicating that the device is not ready to transfer data during high speed clock signal cycles.
References Cited (Backward Citations)
No citation records indexed.
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