Patent US6436796B1 successfully refreshed from Google Patents.
Patent EP0377841A2 successfully refreshed from Google Patents.
EP0377841A2
Expired / Lapsed
EP
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Semiconductor integrated circuit capable of preventing occurrence of erroneous operation due to noise
Assignee: Toshiba Corp
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Filing: 1989-12-12
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Granted: —
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Expires: 2009-12-12
Abstract
Abstract A semiconductor integrated circuit includes a circuit block (13) whose operation is controlled by a inverted control signal whose significant potential level is set at a ground potential, and a wiring (12) for transmitting a control signal for controlling the operation of the circuit block (13). An inverting circuit (14) provided near the circuit block inverts the control signal and then supplies the inverted signal to the circuit block (13) via a wiring (15). The inverter includes a first capacitor (25) connected between the power source terminal and a node (23) which is set at a high potential level in the inverter circuit (14) when the control signal is set at the non-significant potential level and a second capacitor (30) connected between a ground potential terminal and a node (28) which is set at a ground potential level when the control signal is set at the non-significant potential level.
Inventors
- 👤 Nobuaki Intell. Property Div. Ohtsuka
- 👤 Sumio Intell. Property Div. Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 02:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C16/22; G11C16/225
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
106 words
A semiconductor integrated circuit characterized by comprising: a circuit block (13) whose operation is controlled by a first control signal whose significant potential level is set at a ground potential; a wiring (12) for transmitting a second control signal whose significant potential level is set at a potential level corresponding to a power source voltage; control means (11) for supplying the second control signal to said wiring (12); and inverting means (14) provided near said circuit block (13), for inverting the second control signal on said wiring (12) to obtain the first control signal and then supplying the first control signal to said circuit block (13).
Claim 2
Dependent Claim
106 words
A semiconductor integrated circuit characterized by comprising: a circuit block (13) whose operation is controlled by a first control signal whose significant potential level is set at a ground potential; a wiring (12) for transmitting a second control signal whose significant potential level is set at a potential level corresponding to a power source voltage; control means (11) for supplying the second control signal to said wiring (12); and inverting means (14) provided near said circuit block (13), for inverting the second control signal on said wiring (12) to obtain the first control signal and then supplying the first control signal to said circuit block (13).
Claim 3
Dependent Claim
48 words
A circuit according to claim 1, characterized in that said inverting means (14) includes a first capacitor (25) connected between the power source terminal and a node (23) which is set at a high potential level when the second control signal is set at the nonsignificant potential level.
Claim 4
Dependent Claim
20 words
A circuit according to claim 2, characterized in that said first capacitor (25) includes a depletion type MOS transistor (25).
Claim 5
Dependent Claim
51 words
A circuit according to one of claims 1 to 3, characterized in that said inverting means (14) includes a second capacitor (30) connected between a ground potential terminal and a node (28) which is set at a ground potential level when the control signal is set at the non-significant potential level.
Claim 6
Dependent Claim
20 words
A circuit according to claim 4, characterized in that said second capacitor (30) includes a depletion type MOS transistor (30).
Claim 7
Dependent Claim
47 words
A circuit according to one of claims 1 to 5, characterized in that the length of said wiring (12) between said control means (11) and said inverting means (14) is larger than that of said wiring (15) between said inverting means (14) and said circuit block (130).
Claim 8
Dependent Claim
185 words
A circuit according to claim 1, characterized in that said inverting means (14) includes: a first inverter (21) for inverting the control signal on said wiring(12); a first transfer gate (24) of CMOS type connected between the output node of said first inverter (14) and a first node (23) and acting as a resistor; a first MOS transistor (25) of depletion type having a source and a drain connected to said first node (23) and a gate connected to the power source terminal and acting as a capacitor; a second inverter (26) for inverting a signal on said first node (23); a second transfer gate (29) of CMOS type connected between the output node of said second inverter (26) and a second node (28) and acting as a resistor; a second MOS transistor (30) of depletion type having a source and a drain connected to said second node (28) and a gate connected to the ground potential terminal and acting as a capacitor; and a NAND gate (34) for effecting the logic AND operation of a signal on said second node and the control signal.
References Cited (Backward Citations)
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