Semiconductors memory device provided with an improved redundant decoder

Claim 1

A semiconductor memory device comprising a plurality of normal memory cell groups, at least one redundant memory cell group, means for receiving a plurality of address signals, a normal decoder for operatively selecting one of said normal memory cell groups in accordance with said address signals when all of memory cells of one of said normal memory cell groups designated by said address signals are good, and a redundant decoder for operatively selecting said redundant memory cell group when one of said normal memory cell groups designated by said address signals contains at least one defective memory cell, said redundant decoder including a multi-input logic circuit, a plurality of address program circuits, each of said address program circuits having an input end receiving one of said address signal, an output end coupled to one of input terminals of said multi-input logic circuit, first means for generating a complementary signal of the received address signal, and a programmable transfer circuit coupled to said input end, said first means and said output end for applying one of said received address signal and said complementary signal to said output end when enabled and setting said output end at an inactive level when disenabled, a state program circuit assuming a first state when all memory cells of said plurality of memory cell groups are good and a second state when at least one of said normal memory cell groups contains a defective memory cell, and a control circuit for enabling all of said address program circuits in response to said second state of said state program circuit and disenabling all of said address program circuits in response to said first state of said state program circuit.