Processing sampled analogue electrical signals

Claim 2

A circuit arrangement for processing sampled analogue electrical signals, each sample being in the form of a current, the circuit arrangement comprising means for combining in predetermined proportions, the input sample current in the present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods, and means for deriving the processed output signal from the combined current produced by the combining means in successive sample periods, wherein the circuit arangement comprises transistors and all the transistors which conduct signal currents are formed by devices having the same polarity.

Claim 3

A circuit arrangement as claimed in Claim 1, in which the transistors which carry signal currents are formed as n-channel field effect transistors.

Claim 4

A circuit arrangement as claimed in Claim 1 or Claim 2, comprising a plurality of circuit modules, each circuit module having a current input for receiving a bi-directional input signal current and a current output for supplying a bi-directional output signal current, means for adding a bias current to the bi-directional input signal current to produce a uni-directional current for processing by the circuit module, and means for subtracting a suitably scaled bias current from the processed uni-directional current to produce a bi-directional output signal current.

Claim 5

A circuit arrangement as claimed in Claim 3, in which one of the circuit modules comprises a current memory module which is capable of reproducing at its output in one sampling period a scaled version of the current applied to its input in a previous sampling period.

Claim 6

A circuit arrangement as claimed in Claim 4, in which the current memory module comprises a current input, a current output, first and second switches controlled by first and second non-overlapping clock signals, and first and second memory cells, each memory cell comprising a field effect transistor having a capacitor connected between its gate and source electrodes wherein the current input is coupled to the first memory cell by means of the first switch and the first memory cell is coupled to the second memory cell by means of the second switch, the output of the second memory cell being coupled to the current output.

Claim 7

A circuit arrangement as claimed in Claim 4 in which the current memory module includes a first memory cell having an input, an output, means comprising a first switch which is conductive during a first portion of a sample period for connecting the input of the first memory cell to the main current conducting path of a transistor, means comprising a second switch which is conductive during the first portion for connecting the junction of the first switch and the main current conducting path of the transistor to a current maintaining means, and means for connecting the main current conducting path of the transistor to the output of the first memory cell during a second portion of the sampling period, a second memory cell having an input coupled to the output of the first memory cell and an output coupled to the output of the current memory module, and means for coupling the input of the current memory module to the input of the first memory cell, wherein the means for connecting the main current conducting path of the transistor to the output of the first memory cell comprises a switch which is conductive during a second portion of the sampling period which does not overlap the first portion, an output current from the first memory cell being available when the third switch is conductive.

Claim 8

A circuit arrangement as claimed in Claim 4 in which the memory module has differential inputs and outputs and comprises a plurality of current memory cells, means for coupling each of the differential inputs to a respective current memory cell and means for combining the outputs of selected memory cells for application to the differential current outputs.

Claim 9

A circuit arrangement as claimed in Claim 3 including an integrator circuit module which is capable of integrating a bi-directional current applied to its input.

Claim 10

A circuit arrangement as claimed in Claim 8 in which the integrator circuit module comprises a current memory module as claimed in any of Claims 4 to 7 and a feedback loop from a stored current output to a summing arrangement so that a stored current can be added to each current input sample.

Claim 11

A circuit arrangement as claimed in Claim 8 or Claim 9 arranged to integrate differential input currents.

Claim 12

A circuit arrangement as claimed in Claim 1 or Claim 2, comprising a static module which is capable of producing a scaled version of the current applied to its input at its output.

Claim 13

A circuit arrangement as claimed in Claim 11, in which the static module has a plurality of outputs each of which is capable of producing an individually scaled output.

Claim 14

A circuit arrangement as claimed in Claim 11 or 12 in which the static module has a plurality of inputs by means of which a plurality of input currents may be applied to the static module to enable current addition or subtraction to be performed by the static module.

Claim 15

A circuit arrangement as claimed in any of Claims 11 to 13, in which the static module comprises a current scaling circuit, the current scaling circuit comprising means for applying an input current to the input branch of a first current mirror circuit, means for applying a bias current to the input branch of the first current mirror circuit, means for feeding the current from the output branch of the first current mirror circuit to the input branch of a second current mirror circuit, means for feeding the current from the output branch of the second current mirror circuit to the output of the static module, and means for subtracting a suitably scaled bias current from the current produced by the output branch of the second current mirror circuit so that the output current produced by the scaling circuit is a scaled version of the input current applied to the input of the scaling circuit.

Claim 16

A circuit arrangement as claimed in Claim 14, in which the means for applying a bias current to the input branch of the first current mirror circuit comprises a first current source and means for adding the current produced by the first current source to the input current and the means for subtracting a bias current comprises a second current source and a current summing junction to which the output current from the second current source and the output current from the output branch of the second current mirror are applied with appropriate polarity and means for deriving the scaled output current from the summing junction.

Claim 17

A circuit arrangement as claimed in any of Claims 11 to 15 in which the static module is arranged to process a differential input current and produce and differential output current.