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Patent EP0372580A2 successfully refreshed from Google Patents.
EP0372580A2
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EP
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Synchronization of fault-tolerant computer system having multiple processors
Assignee: Tandem Computers Inc
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Filing: 1989-12-08
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Granted: —
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Expires: 2009-12-08
Abstract
Abstract A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.
Inventors
- 👤 Richard W. Cutts, Jr.
- 👤 Douglas E. Jewett
- 👤 Richard A. Southworth
- 👤 Kenneth C. Debacker
- 👤 Nikhil A. Mehta
- 👤 John David Allison
- 👤 Robert W. Horst
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 09:28
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/18; G06F11/183; G06F11/184; G06F11/185; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0724; G06F11/1658; G06F11/1666; G06F11/1675; G06F11/1683; G06F11/1687; G06F11/1691; G06F11/20; G06F11/2017; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/08; G06F11/10; G06F11/1008; G06F11/14; G06F11/1402; G06F11/1405; G06F11/1415; G06F11/1629; G06F11/1641; G06F11/1645; G06F11/1679; G06F11/181; G06F11/182; G06F11/2002; G06F11/2007; G06F11/2015; G06F2201/00; G06F2201/85; G11; G11C; G11C29/00; G11C29/70; G11C29/74
Claims Analysis
Total Claims: 62
Claim 1
Independent Claim
203 words
A multiple CPU system, comprising: a) a plurality of CPUs executing an instruction stream, the CPUs each being clocked independently of one another to provide separate machine cycles for each CPU, said machine cycles including execution cycles where an instruction of said instruction stream is executed and stall cycles where an instruction of said instruction stream is not executed, each CPU having a memory request input/output port; b) a common memory coupled to the input/output ports of said CPUs, the common memory implementing a memory request only after receiving the same request from all of said CPUs, the memory sending an acknowledge signal to the CPUs when implementing a memory request, each of the CPUs executing stall cycles while awaiting implementation of a memory request by the common memory as signalled by said acknowledge signal; c) each of the CPUs having a counter to count execution cycles but not stall cycles; and d) said CPUs having an interrupt circuit responsive to an external interrupt request and coupled to said counters in said CPUs and responsive to a selected count in each of said counters for separately interrupting each CPU at the same execution cycle while other of said CPUs continue to execute instructions.
Claim 2
Dependent Claim
203 words
A multiple CPU system, comprising: a) a plurality of CPUs executing an instruction stream, the CPUs each being clocked independently of one another to provide separate machine cycles for each CPU, said machine cycles including execution cycles where an instruction of said instruction stream is executed and stall cycles where an instruction of said instruction stream is not executed, each CPU having a memory request input/output port; b) a common memory coupled to the input/output ports of said CPUs, the common memory implementing a memory request only after receiving the same request from all of said CPUs, the memory sending an acknowledge signal to the CPUs when implementing a memory request, each of the CPUs executing stall cycles while awaiting implementation of a memory request by the common memory as signalled by said acknowledge signal; c) each of the CPUs having a counter to count execution cycles but not stall cycles; and d) said CPUs having an interrupt circuit responsive to an external interrupt request and coupled to said counters in said CPUs and responsive to a selected count in each of said counters for separately interrupting each CPU at the same execution cycle while other of said CPUs continue to execute instructions.
Claim 3
Dependent Claim
21 words
A system according to claim 1 wherein each of said CPUs has a local memory not accessible by the other CPUs.
Claim 4
Dependent Claim
117 words
A multiple CPU system with synchronization of external interrupts, comprising: a) a plurality of CPUs independently executing the same instruction stream, the CPUs each being clocked independently of one another to provide execution cycles during which instructions of said instruction stream are executed and to provide stall cycles during which instructions are not executed; b) each of the CPUs having a counter to count said execution cycles but not stall cycles; c) and an interrupt circuit connected to all of said CPUs and responsive to an external interrupt request, said interrupt circuit being responsive to a selected count in each of said counters for interrupting each CPU separately at the same execution cycle in said instruction stream.
Claim 5
Dependent Claim
117 words
A multiple CPU system with synchronization of external interrupts, comprising: a) a plurality of CPUs independently executing the same instruction stream, the CPUs each being clocked independently of one another to provide execution cycles during which instructions of said instruction stream are executed and to provide stall cycles during which instructions are not executed; b) each of the CPUs having a counter to count said execution cycles but not stall cycles; c) and an interrupt circuit connected to all of said CPUs and responsive to an external interrupt request, said interrupt circuit being responsive to a selected count in each of said counters for interrupting each CPU separately at the same execution cycle in said instruction stream.
Claim 6
Dependent Claim
36 words
A system according to claim 3 wherein there are three said CPUs, and wherein all three CPUs access a common memory module, requests to said common memory from said CPUs being voted by said memory module.
Claim 7
Dependent Claim
85 words
A multiple CPU system, comprising: a) a plurality of CPUs each executing an instruction stream, the CPUs being clocked independently of one another to provide execution cycles, b) each of the CPUs having a counter to count execution cycles; c) and an interrupt circuit connected to each of said CPUs and responsive to an external interrupt request, said interrupt circuit being responsive to a selected count in each of said counters for separately interrupting each CPU at the same execution cycle in said instruction stream.
Claim 8
Dependent Claim
85 words
A multiple CPU system, comprising: a) a plurality of CPUs each executing an instruction stream, the CPUs being clocked independently of one another to provide execution cycles, b) each of the CPUs having a counter to count execution cycles; c) and an interrupt circuit connected to each of said CPUs and responsive to an external interrupt request, said interrupt circuit being responsive to a selected count in each of said counters for separately interrupting each CPU at the same execution cycle in said instruction stream.
Claim 9
Dependent Claim
36 words
A system according to claim 5 wherein there are three said CPUs, and wherein all three CPUs access a common memory module, requests to said common memory from said CPUs being voted by said memory module.
Claim 10
Dependent Claim
128 words
A multiple CPU system, comprising: a) a plurality of CPUs, each of the CPUs independently executing the same instruction stream, the CPUs being clocked independently of one another to provide execution cycles, the CPUs each having an input/output port, at least one shared input/output device being coupled to said input/output ports of the plurality of CPUs; b) each of the CPUs having a modulo N counter to count execution cycles; c) and an interrupt circuit coupled to each of said CPUs and responsive to an external interrupt request, said interrupt circuit being correlated with said counters for applying an interrupt separately to each CPU at a preset count value of each of the counters, whereby each CPU is interrupted at the same execution cycle in said instruction stream.
Claim 11
Dependent Claim
128 words
A multiple CPU system, comprising: a) a plurality of CPUs, each of the CPUs independently executing the same instruction stream, the CPUs being clocked independently of one another to provide execution cycles, the CPUs each having an input/output port, at least one shared input/output device being coupled to said input/output ports of the plurality of CPUs; b) each of the CPUs having a modulo N counter to count execution cycles; c) and an interrupt circuit coupled to each of said CPUs and responsive to an external interrupt request, said interrupt circuit being correlated with said counters for applying an interrupt separately to each CPU at a preset count value of each of the counters, whereby each CPU is interrupted at the same execution cycle in said instruction stream.
Claim 12
Dependent Claim
36 words
A system according to claim 7 wherein there are three said CPUs, and wherein all three CPUs access a common memory module, requests to said common memory from said CPUs being voted by said memory module.
Claim 13
Dependent Claim
137 words
A computer system comprising: a) a plurality of CPUs each executing an instruction stream, the CPUs being clocked independently of one another to define execution cycles; b) each of the CPUs having counting means to count events related to execution cycles; c) each CPU having a synchronizing circuit responsive to an externally-applied request applied to all of said CPUs, said synchronizing circuit for each CPU receiving input from all of said CPUs, for separately signalling each one of the CPUs at the same point in said instruction stream in response to said externally-applied request, the synchronizing circuit for each of said CPUs also responsive to said counting means indicating a selected maximum count and responsive to information from the other CPUs for causing the CPU to begin execution at the same execution cycle in said instruction stream.
Claim 14
Dependent Claim
137 words
A computer system comprising: a) a plurality of CPUs each executing an instruction stream, the CPUs being clocked independently of one another to define execution cycles; b) each of the CPUs having counting means to count events related to execution cycles; c) each CPU having a synchronizing circuit responsive to an externally-applied request applied to all of said CPUs, said synchronizing circuit for each CPU receiving input from all of said CPUs, for separately signalling each one of the CPUs at the same point in said instruction stream in response to said externally-applied request, the synchronizing circuit for each of said CPUs also responsive to said counting means indicating a selected maximum count and responsive to information from the other CPUs for causing the CPU to begin execution at the same execution cycle in said instruction stream.
Claim 15
Dependent Claim
14 words
A system according to claim 9 wherein said synchronizing request is an external interrupt.
Claim 16
Dependent Claim
30 words
A system according to claim 1 wherein there are three of said CPUs, and wherein said requests to said common memory via said port are voted by said common memory.
Claim 17
Dependent Claim
22 words
A system according to claim 1 wherein said interrupt circuit interrupts said CPUs only on a selected value registered by said counters.
Claim 18
Dependent Claim
40 words
A system according to claim 1 wherein said interrupt circuit includes for each CPU means responsive to an indication of receipt of an interrupt request when a selected value is registered in said counter of each of the other CPUs.
Claim 19
Dependent Claim
21 words
A system according to claim 3 wherein each of sald CPUs has a local memory not accessible by the other CPUs.
Claim 20
Dependent Claim
37 words
A system according to claim 4 wherein there are three of said CPUs, and a common memory accessed by said three CPUs, and accesses to said common memory by the CPUs are voted by said common memory.
Claim 21
Dependent Claim
21 words
A system according to claim 5 wherein each of said CPUs has a local memory not accessible by the other CPUs.
Claim 22
Dependent Claim
36 words
A system according to claim 5 wherein there are three of said CPUs, and wherein each of said CPUs makes access requests to a common memory, and said access requests are voted by said common memory.
Claim 23
Dependent Claim
37 words
A system according to claim 5 wherein said interrupt circuit includes for each CPU means responsive to receipt of an interrupt request when a selected value is registered in said counter of each of the other CPUs.
Claim 24
Dependent Claim
15 words
A system according to claim 7 wherein said shared input/output device is a common memory.
Claim 25
Dependent Claim
38 words
A system according to claim 7 wherein said interrupt circuit interrupts each of said CPUs when a selected value is registered by said counter for each CPU without stalling execution of instructions by faster ones of said CPUs.
Claim 26
Dependent Claim
37 words
A system according to claim 7 wherein said interrupt circuit includes for each CPU means responsive to receipt of an interrupt request when a selected value is registered in said counter of each of the other CPUs.
Claim 27
Dependent Claim
21 words
A system according to claim 7 wherein each of said CPUs has a local memory not accessible by the other CPUs.
Claim 28
Independent Claim
71 words
A method of operating a computer system having a plurality of separately-clocked CPUs, comprising the steps of: a) executing the same instruction stream on each of said CPUs; b) counting the instructions executed on each of said CPUs; c) detecting an external interrupt request and applying an interrupt signal separately to each one of the CPUs at a selected instruction count while the other of the CPUs continue to execute instructions.
Claim 29
Independent Claim
71 words
A method of operating a computer system having a plurality of separately-clocked CPUs, comprising the steps of: a) executing the same instruction stream on each of said CPUs; b) counting the instructions executed on each of said CPUs; c) detecting an external interrupt request and applying an interrupt signal separately to each one of the CPUs at a selected instruction count while the other of the CPUs continue to execute instructions.
Claim 30
Dependent Claim
31 words
A method according to claim 23 including the step of making memory access requests by said CPUs to a common memory and voting each of said requests by sald common memory.
Claim 31
Dependent Claim
33 words
A method according to claim 24 including the step of accessing a local memory separately by each of said CPUs, the local memory for each CPU not being accessible by the other CPUs.
Claim 32
Dependent Claim
27 words
A method according to claim 23 wherein said step of detecting an external interrupt request is performed only at a selected value of said count of instructions.
Claim 33
Dependent Claim
92 words
Apparatus for synchronizing a plurality of processors, comprising: event detecting means in each one of said processors producing an indication of the occurrence of a selected type of event within the processor; event counting means responsive to said indication for counting the number of events for each one of said processors; and means responsive to said event counting means for altering processing of each one of said processors if the number of events counted for one of the processors is greater than the number of events counted for other of said processors.
Claim 34
Dependent Claim
92 words
Apparatus for synchronizing a plurality of processors, comprising: event detecting means in each one of said processors producing an indication of the occurrence of a selected type of event within the processor; event counting means responsive to said indication for counting the number of events for each one of said processors; and means responsive to said event counting means for altering processing of each one of said processors if the number of events counted for one of the processors is greater than the number of events counted for other of said processors.
Claim 35
Dependent Claim
23 words
Apparatus according to claim 27 wherein said selected type of circuit is a machine cycle in the processor in which the pipeline advances.
Claim 36
Dependent Claim
13 words
Apparatus according the claim 28 wherein sald event counter is a cycle counter.
Claim 37
Dependent Claim
52 words
Apparatus according to claim 27 including sync-request means receiving a synchronization request signal, and wherein the means for suspending suspends processing of a processor in response to the synchronization request signal when the number of events counted for that processor is not less than the number of events counted for another processor.
Claim 38
Dependent Claim
13 words
Apparatus according to claim 30 wherein said synchronization request signal is an interrupt.
Claim 39
Dependent Claim
23 words
Apparatus according to claim 28 including means for restarting a suspended processor when the number of events counted for each processor is equal.
Claim 40
Dependent Claim
37 words
Apparatus according to claim 29 wherein the means for suspending suspends processing of a processor when the number of events counted for that processor is not less than the number of events counted for a suspended processor.
Claim 41
Dependent Claim
97 words
Apparatus for synchronlzing a plurality of processors comprising, for each processor: event counting means, connected to the processor for counting the number of occurrences of a prescribed event; comparison means connected for receiving signals for the event counting means for each processor; and synchronization means, connected to receive a sync request input signal and to the event counter, and responsive to said comparison means, for suspending processing of a processor in response to a synchronization request signal until the number of events counted to each processor is equal to the number of events counted for other processors.
Claim 42
Dependent Claim
97 words
Apparatus for synchronlzing a plurality of processors comprising, for each processor: event counting means, connected to the processor for counting the number of occurrences of a prescribed event; comparison means connected for receiving signals for the event counting means for each processor; and synchronization means, connected to receive a sync request input signal and to the event counter, and responsive to said comparison means, for suspending processing of a processor in response to a synchronization request signal until the number of events counted to each processor is equal to the number of events counted for other processors.
Claim 43
Dependent Claim
37 words
Apparatus according to claim 34 wherein the prescribed event is a clock cycle of the processor in which an instruction is executed, and wherein said clock cycle is one in which the pipeline of the processor advances.
Claim 44
Dependent Claim
23 words
Apparatus according to claim 34 wherein the sync request input is an interrupt, and wherein the event counting means is a cycle counter.
Claim 45
Dependent Claim
71 words
A fault-tolerant computer system comprising: a) multiple processors, each executing the same instruction stream, each processor having an independent clock, and each processor having a memory independent of the other processors; b) a plurality of vote circuits, each one of the vote circuits separately receiving output data from each one of the processors, and producing a voter output to I/O means only when multiple processors have sent the same data output.
Claim 46
Dependent Claim
71 words
A fault-tolerant computer system comprising: a) multiple processors, each executing the same instruction stream, each processor having an independent clock, and each processor having a memory independent of the other processors; b) a plurality of vote circuits, each one of the vote circuits separately receiving output data from each one of the processors, and producing a voter output to I/O means only when multiple processors have sent the same data output.
Claim 47
Dependent Claim
26 words
A system according to claim 37 wherein said processors are loosely synchronized by counting cycles of operation of the processors and stalling processors ahead of others.
Claim 48
Dependent Claim
29 words
A system according to claim 37 including input buffers coupling each said I/O means to each one of said processors, the processors accepting data from said input buffers asynchronously.
Claim 49
Dependent Claim
39 words
A system according to claim 37 wherein said output data from each processor is held in an output buffer until all said processor have loaded output data to their output buffer, and wherein said output buffer is a FIFO.
Claim 50
Independent Claim
95 words
A method of operating a multiple processor system comprising the steps of: a) clocking each of said processors independent of one another; b) executing the same instruction stream in each one of the processors; c) storing data for each processor in a separate memory not accessible by the other processors; d) presenting output data to an output port of each processor; e) detecting the output data in all said ports in a vote circuit and voting said output data to pass on the output data that is the same from multiple processors to I/O means.
Claim 51
Independent Claim
95 words
A method of operating a multiple processor system comprising the steps of: a) clocking each of said processors independent of one another; b) executing the same instruction stream in each one of the processors; c) storing data for each processor in a separate memory not accessible by the other processors; d) presenting output data to an output port of each processor; e) detecting the output data in all said ports in a vote circuit and voting said output data to pass on the output data that is the same from multiple processors to I/O means.
Claim 52
Dependent Claim
33 words
A method according to claim 41 including the step of storing said output data in a buffer at each one of said ports, and wherein each one of said buffers is a FIFO.
Claim 53
Dependent Claim
28 words
A method according to claim 42 including the step of loosely synchronlzing said processors by counting cycles of operation of the processors and stalling processors ahead of others.
Claim 54
Independent Claim
94 words
A method of operating a computer system comprising the steps of: a) executing the same instruction stream in at least first and second processors; b) generating remote accesses in each of said first and second processors, the remote accesses being directed to separate first and second access ports; c) detecting each one of said remote accesses at said first and second access ports, waiting until a remote access is detected at both the first and second access ports, then voting said remote accesses and passing along said remote accesses if both are the same.
Claim 55
Independent Claim
94 words
A method of operating a computer system comprising the steps of: a) executing the same instruction stream in at least first and second processors; b) generating remote accesses in each of said first and second processors, the remote accesses being directed to separate first and second access ports; c) detecting each one of said remote accesses at said first and second access ports, waiting until a remote access is detected at both the first and second access ports, then voting said remote accesses and passing along said remote accesses if both are the same.
Claim 56
Dependent Claim
41 words
A method according to claim 44 wherein said step of executing is in independently-clocked processors, and wherein said step of generating remote accesses in said first and second processors includes temporarily storing said remote accesses in a buffer for each processor.
Claim 57
Dependent Claim
71 words
A method according to claim 44 wherein said first and second access ports are in first and second modules operated asynchronous to said first and second processors, and wherein said first and second processors are loosely synchronized by counting cycles of operation and stalling a processor ahead of the other; and including the step of storing data for sald first and second processors in separate memories accessible by only one processor.
Claim 58
Dependent Claim
91 words
A computer system comprising: a) first and second processors executing the same instruction stream; b) means generating remote accesses in each of said first and second processors, the remote accesses being directed to separate first and second access ports; c) separate voter means detecting each one of said remote accesses at said first and second access ports, the voter means waiting until a remote access is detected at both the first and second access ports before voting said remote accesses and passing along said remote accesses if both are the same.
Claim 59
Dependent Claim
91 words
A computer system comprising: a) first and second processors executing the same instruction stream; b) means generating remote accesses in each of said first and second processors, the remote accesses being directed to separate first and second access ports; c) separate voter means detecting each one of said remote accesses at said first and second access ports, the voter means waiting until a remote access is detected at both the first and second access ports before voting said remote accesses and passing along said remote accesses if both are the same.
Claim 60
Dependent Claim
24 words
A system according to claim 47 wherein said processors are independently clocked; and including a buffer for each processor temporarily storing said remote accesses.
Claim 61
Dependent Claim
27 words
A system according to claim 47 wherein said first and second access ports are in first and second modules operated asynchronous to said first and second processors.
Claim 62
Dependent Claim
27 words
A system according to claim 47 including separate memory means for each one of said first and second processors, each memory means accessible by only one processor.
References Cited (Backward Citations)
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