Patent EP0371418A2 successfully refreshed from Google Patents.
EP0371418A2
Expired / Lapsed
EP
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Apparatus for and method of providing the program counter of a microprocessor external to the device
Assignee: National Semiconductor Corp
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Filing: 1989-11-25
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Granted: —
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Expires: 2009-11-25
Abstract
Abstract A microprocessor's program counter is made available external to the device on a dedicated bus. Thus, an emulator can readily generate a list of executed instruction addresses by monitoring the bus. This eliminates the conventional requirement of monitoring system bus traffic and attempting to extract and reconstruct the instruction execution sequence.
Inventors
- 👤 Bruce B. Razban
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 05:32
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/30; G06F11/34; G06F11/3648; G06F11/3656
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
51 words
In a data processing device of the type that executes a sequence of instructions and includes a program counter register that contains the address of the instruction currently being executed by the device, the improvement comprising a bus that provides the contents of the program counter register external to the device.
Claim 2
Dependent Claim
51 words
In a data processing device of the type that executes a sequence of instructions and includes a program counter register that contains the address of the instruction currently being executed by the device, the improvement comprising a bus that provides the contents of the program counter register external to the device.
Claim 3
Dependent Claim
53 words
A microprocessor device of the type that executes a sequence of program instructions, the microprocessor device comprising: (a) a program counter register that contains the address of the instruction currently being executed by the microprocessor device; and (b) means for providing the contents of the program counter register external to the microprocessor device.
Claim 4
Dependent Claim
53 words
A microprocessor device of the type that executes a sequence of program instructions, the microprocessor device comprising: (a) a program counter register that contains the address of the instruction currently being executed by the microprocessor device; and (b) means for providing the contents of the program counter register external to the microprocessor device.
Claim 5
Dependent Claim
88 words
A microprocessor device that includes means for executing a sequence of program instructions, the microprocessor device comprising: (a) a program counter register that contains the address of the instruction currently being executed by the microprocessor device; (b) buffer means; and (c) a dedicated external bus that receives the contents of the program counter register via the buffer means whereby the address of each executed instruction is externally available via the external bus such that the sequence of program instruction execution can be externally monitored via the external bus.
Claim 6
Dependent Claim
88 words
A microprocessor device that includes means for executing a sequence of program instructions, the microprocessor device comprising: (a) a program counter register that contains the address of the instruction currently being executed by the microprocessor device; (b) buffer means; and (c) a dedicated external bus that receives the contents of the program counter register via the buffer means whereby the address of each executed instruction is externally available via the external bus such that the sequence of program instruction execution can be externally monitored via the external bus.
Claim 7
Dependent Claim
27 words
A microprocessor device as in Claim 3 wherein the bit size of the program counter register is the same as the bit size of the external bus.
Claim 8
Dependent Claim
30 words
A microprocessor device as in Claim 3 and further including means for making the contents of the program counter register available on the dedicated external bus in multiple consecutive cycles.
Claim 9
Dependent Claim
47 words
A microprocessor device as in Claim 3 wherein the program counter register is a 32 bit register and the dedicated external bus is a 16 bit bus and the microprocessor device includes means for making the contents of the program counter register available on two consecutive cycles.
Claim 10
Dependent Claim
105 words
A microprocessor device of the type that executes a sequence of program instructions, the microprocessor device comprising: (a) means for referencing the virtual address of a program instruction; (b) means for translating the virtual address to a corresponding physical address of a storage location in external memory that contains the program instruction; (c) means for retrieving the program instruction from external memory; (d) means for executing the program instruction; (e) means for storing the virtual address of the program instruction being executed; (f) a dedicated external bus; and (g) means for transferring the virtual address of the executing program instruction to the dedicated external bus.
Claim 11
Dependent Claim
105 words
A microprocessor device of the type that executes a sequence of program instructions, the microprocessor device comprising: (a) means for referencing the virtual address of a program instruction; (b) means for translating the virtual address to a corresponding physical address of a storage location in external memory that contains the program instruction; (c) means for retrieving the program instruction from external memory; (d) means for executing the program instruction; (e) means for storing the virtual address of the program instruction being executed; (f) a dedicated external bus; and (g) means for transferring the virtual address of the executing program instruction to the dedicated external bus.
Claim 12
Independent Claim
48 words
A method of monitoring the sequence of program instructions executed by a data processing system, the method comprising: (a) storing the address of the instruction presently being executed by the data processing system; (b) transferring the stored address to a dedicated external bus of the data processing system.
Claim 13
Independent Claim
48 words
A method of monitoring the sequence of program instructions executed by a data processing system, the method comprising: (a) storing the address of the instruction presently being executed by the data processing system; (b) transferring the stored address to a dedicated external bus of the data processing system.
Claim 14
Independent Claim
83 words
A method of monitoring the sequence of program instructions executed by a microprocessor device, the method comprising: (a) referencing the virtual address of a program instruction; (b) translating the virtual address to a corresponding physical address of a storage location in external memory that contains the program instruction; (c) retrieving the program instruction from external memory; (d) executing the program instruction; (e) storing the virtual address of the executing program instruction; and (f) transferring the stored virtual address to an external dedicated bus.
Claim 15
Independent Claim
83 words
A method of monitoring the sequence of program instructions executed by a microprocessor device, the method comprising: (a) referencing the virtual address of a program instruction; (b) translating the virtual address to a corresponding physical address of a storage location in external memory that contains the program instruction; (c) retrieving the program instruction from external memory; (d) executing the program instruction; (e) storing the virtual address of the executing program instruction; and (f) transferring the stored virtual address to an external dedicated bus.
Claim 16
Dependent Claim
22 words
A method as in Claim 9 wherein the stored virtual address is transferred to the external dedicated bus in a single cycle.
Claim 17
Dependent Claim
22 words
A method as in Claim 9 wherein the stored virtual address is transferred to the external dedicated bus in multiple, consecutive cycles.
References Cited (Backward Citations)
No citation records indexed.
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