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EP0370194A2
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Reconfigurable register bit slice
Assignee: Honeywell Inc
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Filing: 1989-09-20
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Granted: —
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Expires: 2009-09-20
Abstract
Abstract A re-configurable register bit-slice is disclosed for use in built-in logic block observers (i.e. BILBOs). The register bit-slice (40) may be configured to a plurality of operational modes. Front-end logic (42) is disclosed which switches a single current switch (e.g. transistor) between a data input and an output of the front-end logic. Thus, a single current switch of delay is added to normal operation of a standard shift register modified to be reconfigurable.
Inventors
- 👤 Charles L. Hudson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 18:40
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318547; G11; G11C; G11C19/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
258 words
A register bit-slice, characterized by : a) memory means (44) for storing a bit, the memory means comprising an input (D) for receiving a data signal; and b) front-end logic means (42, 60, 120), comprising: (i) an output (148, 150) logically coupled to the input (D) of the memory means (44); (ii) control input means (72, 100; 132, 160) for receiving one or more control input signals (CTRL1; CTRL2); (iii) first data input means (68, 128) for receiving a first data input signal (D IN ); (iv) second data input means (92, 132) for receiving a second data input signal (S IN ); (v) a current switch; (vi) means (70, 84; 128, 144) for operating in a first operational mode by logically coupling the first data input means to the input of the memory means while switching at most one current switch (74, 82; 134, 142) along a signal path from the first data input means to the input of the memory means; (vii) means (94; 154) for operating in a second operational mode by logically coupling the second data input means to the input of the memory means; (viii) means (70, 84, 94; 128, 144, 154) for operating in a third operational mode by providing to the input of the memory means a logical function generated from the input signals received from the first and second data input means; and (ix) means (74, 82, 100; 134, 142, 162) for selectively configuring to one of the operational modes based on the one or more control signals (CTRL1; CTRL2).
Claim 2
Dependent Claim
258 words
A register bit-slice, characterized by : a) memory means (44) for storing a bit, the memory means comprising an input (D) for receiving a data signal; and b) front-end logic means (42, 60, 120), comprising: (i) an output (148, 150) logically coupled to the input (D) of the memory means (44); (ii) control input means (72, 100; 132, 160) for receiving one or more control input signals (CTRL1; CTRL2); (iii) first data input means (68, 128) for receiving a first data input signal (D IN ); (iv) second data input means (92, 132) for receiving a second data input signal (S IN ); (v) a current switch; (vi) means (70, 84; 128, 144) for operating in a first operational mode by logically coupling the first data input means to the input of the memory means while switching at most one current switch (74, 82; 134, 142) along a signal path from the first data input means to the input of the memory means; (vii) means (94; 154) for operating in a second operational mode by logically coupling the second data input means to the input of the memory means; (viii) means (70, 84, 94; 128, 144, 154) for operating in a third operational mode by providing to the input of the memory means a logical function generated from the input signals received from the first and second data input means; and (ix) means (74, 82, 100; 134, 142, 162) for selectively configuring to one of the operational modes based on the one or more control signals (CTRL1; CTRL2).
Claim 3
Dependent Claim
18 words
Register bit-slice according to claim 1, characterized in that the memory means comprises a bi-stable multi-vibrator (44, 180).
Claim 4
Dependent Claim
14 words
Register bit-slice according to claim 1, characterized by emitter-coupled-logic (ECL) design structures (Fig. 4).
Claim 5
Dependent Claim
14 words
Register bit-slice according to claim 1, characterized by current-mode-logic (CML) design structures (Fig. 3).
Claim 6
Dependent Claim
47 words
Register bit-slice according to claim 1, characterized in that the means for operating in a third operational mode comprises means for providing to the input of the memory means an XOR logical function generated from the input signals received from the first and second data input means.
Claim 7
Dependent Claim
45 words
Register bit-slice according to claim 1, characterized in that the control input means comprises a first control input means (72; 132) for receiving a first control input signal (CTRL1) and a second control input means (100; 160) for receiving a second control input signal (CTRL2).
Claim 8
Dependent Claim
73 words
Register bit-slice according to claim 1, characterized by logic level adjust means for adjusting the output signal provided by the output of the front-end logic means to a level acceptable to the input of the memory means, the logic level adjust means comprising an input for providing a logical coupling to the output of the front-end logic means and an output for providing a logical coupling to the input of the memory means.
Claim 9
Dependent Claim
105 words
Register bit-slice comprising a memory means (44) for storing a bit with said memory means comprising an input (D) for receiving a data signal, characterized by a front-end logic means (42, 60, 120) coupled with its output to said input (D) of said memory means (44) and implementing the following logic function (D IN + CTRL1) XOR ( S IN + CTRL2 ) where D IN is a first data input signal of said logic; S IN is a second data input signal of said logic; CTRL1 is a first control signal of said logic; and CTRL2 is a second control signal of said logic.
Claim 10
Dependent Claim
105 words
Register bit-slice comprising a memory means (44) for storing a bit with said memory means comprising an input (D) for receiving a data signal, characterized by a front-end logic means (42, 60, 120) coupled with its output to said input (D) of said memory means (44) and implementing the following logic function (D IN + CTRL1) XOR ( S IN + CTRL2 ) where D IN is a first data input signal of said logic; S IN is a second data input signal of said logic; CTRL1 is a first control signal of said logic; and CTRL2 is a second control signal of said logic.
Claim 11
Dependent Claim
65 words
Register bit-slice according to claim 8, characterized by an OR gate (46) combining said first data input signal (D IN ) and said first control signal (CTRL1), a NOR gate (48) combining said second data input signal (S IN ) and said second control signal (CTRL2) and a XOR gate (50) combining the outputs of said OR gate (40) and of said NOR gate (48).
References Cited (Backward Citations)
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