Abstract A semi-conductor non-volatile memory comprises a semi-conductor substrate (1) of a first conductivity type, a semi-conductor region (8) of the first conductivity type formed in a surface portion of the semi-conductor substrate and having an impurity density higher than that of the semi-conductor substrate, and source and drain regions (2, 3) of a second conductivity type formed in spaced relation in the surface of the semi-conductor substrate. A floating gate electrode (5) is formed on and electrically insulated from the semi-conductor region, and a control gate electrode (7) is formed on and electrically insulated from the floating gate electrode. The memory is characterised by a further semi-conductor region (9) formed inside the first semi-conductor region and containing impurity of the second conductivity type.
A semi-conductor non-volatile memory comprising a semi-conductor substrate (1) of a first conductivity type, a semi-conductor region (8) of the first conductivity type formed in a surface portion of the semi-conductor substrate and having an impurity density higher than that of the semi-conductor substrate, source and drain regions (2, 3) of a second conductivity type formed in spaced relation in the surface of the semi-conductor substrate, a floating gate electrode (5) formed on and electrically insulated from the semi-conductor region, a control gate electrode (7) formed on and electrically insulated from the floating gate electrode, and characterised by a further semi-conductor region (9) formed inside the first semi-conductor region and containing impurity of the second conductivity type.
Claim 2
Dependent Claim
117 words
A semi-conductor non-volatile memory comprising a semi-conductor substrate (1) of a first conductivity type, a semi-conductor region (8) of the first conductivity type formed in a surface portion of the semi-conductor substrate and having an impurity density higher than that of the semi-conductor substrate, source and drain regions (2, 3) of a second conductivity type formed in spaced relation in the surface of the semi-conductor substrate, a floating gate electrode (5) formed on and electrically insulated from the semi-conductor region, a control gate electrode (7) formed on and electrically insulated from the floating gate electrode, and characterised by a further semi-conductor region (9) formed inside the first semi-conductor region and containing impurity of the second conductivity type.
Claim 3
Dependent Claim
38 words
A memory according to claim 1 characterised in that the control gate electrode includes a section capacitively coupled to the floating gate electrode so as to control indirectly a channel region defined between the source and drain regions.
Claim 4
Dependent Claim
35 words
A memory according to claim 2 characterised in that the control gate electrode includes another section formed over and electrically insulated from a part of the channel region so as to control the same directly.
Claim 5
Dependent Claim
42 words
A memory according to claim 3 characterised by a third semi-conductor region (21) formed under said another section and containing impurity of the first conductivity type effective to cancel the impurity of the second conductivity type contained in the further semi-conductor region.
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