Address transition detector circuit

Claim 2

An address transition detector circuit for detecting a transition of an address signal and for outputting a transition detection signal, said address transition detector circuit comprising a first gate circuit (10 having first and second input terminals for receiving a first address signal at the first input terminal, a second gate circuit (11) having third and fourth input terminals for receiving a second address signal at the third input terminal, said first and second address signals being derived from the same address signal but having mutually different phases, a first load (Z1) for feeding back an output signal of said first gate circuit to the fourth input terminal, a second load (Z2) for feeding back an output signal of said second gate circuit to the second input terminal, a third gate circuit (12, 13) supplied with the output signals of said first and second gate circuits, said third gate circuit comprising first and second field effect transistors (12, 13) which are connected in series between first and second nodes, said output signal of said first gate circuit being supplied to a gate of said first field effect transistor (12) and said output signal of said second gate circuit being supplied to a gate of said second field effect transistor (13) so that said first and second field effect transistors are simultaneously turned ON for a predetermined time when said first and second address signals undergo a transition, and first and second power sources (V DD , GND) respectively for generating first and second power source voltages, and characterized in that there is provided: means (Q1, Q10, Z4, Z3) coupled to said first and second nodes and to said first and second power sources (V DD , GND) for pulling a potential at said first node towards the second power source voltage to a first logic level when both said first and second field effect transistors (12, 13) are turned ON and for pulling the potential at said first node towards the first power source voltage to a second logic level when one of said first and second field effect transistors thereafter turn OFF; that said means includes a bipolar transistor (Q1, 010) for pulling the potential at said first node towards the second power source voltage when said bipolar transistor is ON and a third load (Z4) for discharging a base charge of said bipolar transistor towards the second power source voltage when said bipolar transistor is OFF; and that a transition detection signal indicative of the transition of said first and second address signals is obtained from said bipolar transistor.

Claim 3

The address transition detector circuit as claimed in claim 1, characterized in that said means (01, Z4, Z3) further comprises a fourth load (Z3) which is coupled between said first node and said first power source (V DD ), said bipolar transistor (Q1) being an npn type bipolar transistor (Ql) having a base connected to said second node, a collector connected to said first node and an emitter coupled to said second power source (GND), said transition detection signal being obtained from said first node.

Claim 4

An address transition detector circuit for detecting a transition of an address signal and for outputting a transition detection signal, said address transition detector circuit comprising a first gate circuit (10) having first and second input terminals for receiving a first address signal at the first input terminal, a second gate circuit (11) having third and fourth input terminals for receiving a second address signal at the third input terminal, said first and second address signals being derived from the same address signal but having mutually different phases, a first load (Z1) for feeding back an output signal of said first gate circuit to the fourth input terminal, a second load (Z2) for feeding back an output signal of said second gate circuit to the second input terminal, a third gate circuit (12, 13) supplied with the output signals of said first and second gate circuits, said third gate circuit comprising first and second field effect transistors (12, 13) which are connected in series between first and second nodes said output signal of said first gate circuit being supplied to a gate of said first field effect transistor (12) and said output signal of said second gate circuit being supplied to a gate of said second field effect transistor (13) so that said first and second field effect transistors are simultaneously turned ON for a predetermined time when said first and second address signals undergo a transition, and first and second power sources (V oo , GND) respectively for generating first and second power source voltages, and characterized in that there is provided: means (01, Q10, Z4, Z3) coupled to said first and second nodes and to said first and second power sources (Vεα, GND) for pulling a potential at said first node towards the second power source voltage to a first logic level when both said first and second field effect transistors (12, 13) are turned ON and for pulling the potential at said first node towards the first power source voltage to a second logic level when one of said first and second field effect transistors thereafter turn OFF; that said means includes a bipolar transistor (Q1, Q10) for pulling the potential at said first node towards the second power source voltage when said bipolar transistor is ON and a third load (Z4) for discharging a base charge of said bipolar transistor towards the first power source voltage when said bipolar transistor is OFF; and that a transition detection signal indicative of the transition or said first and second address signals is obtained from said bipolar transistor.

Claim 5

An address transition detector circuit for detecting a transition of an address signal and for outputting a transition detection signal, said address transition detector circuit comprising a first gate circuit (10) having first and second input terminals for receiving a first address signal at the first input terminal, a second gate circuit (11) having third and fourth input terminals for receiving a second address signal at the third input terminal, said first and second address signals being derived from the same address signal but having mutually different phases, a first load (Z1) for feeding back an output signal of said first gate circuit to the fourth input terminal, a second load (Z2) for feeding back an output signal of said second gate circuit to the second input terminal, a third gate circuit (12, 13) supplied with the output signals of said first and second gate circuits, said third gate circuit comprising first and second field effect transistors (12, 13) which are connected in series between first and second nodes said output signal of said first gate circuit being supplied to a gate of said first field effect transistor (12) and said output signal of said second gate circuit being supplied to a gate of said second field effect transistor (13) so that said first and second field effect transistors are simultaneously turned ON for a predetermined time when said first and second address signals undergo a transition, and first and second power sources (V oo , GND) respectively for generating first and second power source voltages, and characterized in that there is provided: means (01, Q10, Z4, Z3) coupled to said first and second nodes and to said first and second power sources (Vεα, GND) for pulling a potential at said first node towards the second power source voltage to a first logic level when both said first and second field effect transistors (12, 13) are turned ON and for pulling the potential at said first node towards the first power source voltage to a second logic level when one of said first and second field effect transistors thereafter turn OFF; that said means includes a bipolar transistor (Q1, Q10) for pulling the potential at said first node towards the second power source voltage when said bipolar transistor is ON and a third load (Z4) for discharging a base charge of said bipolar transistor towards the first power source voltage when said bipolar transistor is OFF; and that a transition detection signal indicative of the transition or said first and second address signals is obtained from said bipolar transistor.

Claim 6

The address transition detector circuit as claimed in claim 3, characterized in that said means (Q10, Z4, Z3) further comprises a fourth load (Z3), said bipolar transistor (Q10) being a pnp type bipolar transistor (Q10) having a base connected to said first node, a collector coupled to said second power source (GND) and an emitter which is coupled to said first power source (V oo ) through said fourth load, said transition detection signal being obtained from a node which connects said fourth load and the emitter of said bipolar transistor.

Claim 7

The address transition detector circuit as claimed in any of claims 1 to 4, characterized in that there is further provided an inverter (18) for inverting the transition detection signal which is output from said means (01, 010, Z4, Z3).

Claim 8

An address transition detector circuit for detecting a transition of an address signal and for outputting a transition detection signal, said address transition detector circuit comprising a plurality of detection circuits (17 0 -17 n ) each supplied with two address signal bits which are both derived from the same bit of the address signal but have mutually different phases, first and second power sources (V DD , GND) respectively for generating first and second power source voltages, a first node (NNP) which connects outputs of said detection circuits, and a first load (R3) which is connected between said first power source and said first node, an arbitrary one of said detection circuits comprising a first gate circuit (10) having first and second input terminals for receiving a first address signal bit at the first input terminal, a second gate circuit (11) having third and fourth input terminals for receiving a second address signal bit at the third input terminal, said first and second address signal bits being derived from the same address signal bit but having mutually different phases, a second load (Z1) for feeding back an output signal of said first gate circuit to the fourth input terminal, a third load (Z2) for feeding back an output signal of said second gate circuit to the second input terminal, a third gate circuit (12, 13) supplied with the output signals of said first and second gate circuits, said third gate circuit comprising first and second field effect transistors (12, 13) which are connected in series between second and third nodes, said output signal of said first gate circuit being supplied to a gate of said first field effect transistor and said output signal of said second gate circuit being supplied to a gate of said second field effect transistor so that said first and second field effect transistors are simultaneously turned ON for a predetermined time when said first and second address signals undergo a transition, characterized in that said arbitrary detection circuit is further provided with means (Q1, Q10, Z4) coupled to said first and second nodes and to said first and second power sources (V oo , GND) for pulling a potential at said second node towards the second power source voltage to a first logic level when both said first and second field effect transistors (12, 13) are turned ON and for pulling the potential at said second node towards the first power source voltage to a second logic level when one of said first and second field effect transistors thereafter turn OFF; that said means includes a bipolar transistor (Q1, Q10) for pulling the potential at said second node towards the second power source voltage when said bipolar transistor is ON and a fourth load (Z4) for discharging a base charge of said bipolar transistor towards the second power source voltage when said bipolar transistor is OFF; that a detection signal indicative of a transition in the first and second address signal bits is obtained from said bipolar transistor and supplied to said first node; and that a transition detection signal indicative of a transition in at least one of the address signal bits is obtained from said first node (NNP).

Claim 9

An address transition detector circuit for detecting a transition of an address signal and for outputting a transition detection signal, said address transition detector circuit comprising a plurality of detection circuits (17 0 -17 n ) each supplied with two address signal bits which are both derived from the same bit of the address signal but have mutually different phases, first and second power sources (V DD , GND) respectively for generating first and second power source voltages, a first node (NNP) which connects outputs of said detection circuits, and a first load (R3) which is connected between said first power source and said first node, an arbitrary one of said detection circuits comprising a first gate circuit (10) having first and second input terminals for receiving a first address signal bit at the first input terminal, a second gate circuit (11) having third and fourth input terminals for receiving a second address signal bit at the third input terminal, said first and second address signal bits being derived from the same address signal bit but having mutually different phases, a second load (Z1) for feeding back an output signal of said first gate circuit to the fourth input terminal, a third load (Z2) for feeding back an output signal of said second gate circuit to the second input terminal, a third gate circuit (12, 13) supplied with the output signals of said first and second gate circuits, said third gate circuit comprising first and second field effect transistors (12, 13) which are connected in series between second and third nodes, said output signal of said first gate circuit being supplied to a gate of said first field effect transistor and said output signal of said second gate circuit being supplied to a gate of said second field effect transistor so that said first and second field effect transistors are simultaneously turned ON for a predetermined time when said first and second address signals undergo a transition, characterized in that said arbitrary detection circuit is further provided with means (Q1, Q10, Z4) coupled to said first and second nodes and to said first and second power sources (V oo , GND) for pulling a potential at said second node towards the second power source voltage to a first logic level when both said first and second field effect transistors (12, 13) are turned ON and for pulling the potential at said second node towards the first power source voltage to a second logic level when one of said first and second field effect transistors thereafter turn OFF; that said means includes a bipolar transistor (Q1, Q10) for pulling the potential at said second node towards the second power source voltage when said bipolar transistor is ON and a fourth load (Z4) for discharging a base charge of said bipolar transistor towards the second power source voltage when said bipolar transistor is OFF; that a detection signal indicative of a transition in the first and second address signal bits is obtained from said bipolar transistor and supplied to said first node; and that a transition detection signal indicative of a transition in at least one of the address signal bits is obtained from said first node (NNP).

Claim 10

7 . The address transition detector circuit as claimed in claim 6 , characterized in that said bipolar transistor (Q1) is an npn type bipolar transistor (Q1) having a base connected to said third node, a collector connected to said second node and an emitter coupled to said second power source (GND), said transition detection signal being obtained from said second node.

Claim 11

An address transition detector circuit for detecting a transition of an address signal and for outputting a transition detection signal, said address transition detector circuit comprising a plurality of detection circuits (17 0 -17 n ) each supplied with two address signal bits which are both derived from the same bit of the address signal but have mutually different phases, first and second power sources (V oo , GND) respectively for generating first and second power source voltages, a first node (NNP) which connects outputs of said detection circuits, and a first load (R3) which is connected between said first power source and said first node, an arbitrary one of said detection circuits comprising a first gate circuit (10) having first and second input terminals for receiving a first address signal bit at the first input terminal, a second gate circuit (11) having third and fourth input terminals for receiving a second address signal bit at the third input terminal, said first and second address signal bits being derived from the same address signal bit but having mutually different phases, a second load (ZI) for feeding back an output signal of said first gate circuit to the fourth input terminal, a third load (Z2) for feeding back an output signai of said second gate circuit to the second input terminal, a third gate circuit (12, 13) supplied with the ouyput signals of said first and second gate circuits, said third gate circuit comprising first and second field effect transistors (12, 13) which are connected in series between second and third nodes, said output signal of said first gate circuit being supplied to a gate of said first field effect transistor and said output signal of said second gate circuit being supplied to a gate of said second field effect transistor so that said first and second field effect transistors are simultaneously turned ON for a predetermined time when said first and second address signals undergo a transition, characterized in that said arbitrary detection circuit is further provided with means (01, Q10, Z4) coupled to said first and second nodes and to said first and second power sources (V DD , GND) for pulling a potential at said second node towards the second power source voltage to a first logic level when both said first and second field effect transistors (12, 13) are turned ON and for pulling the potential at said second node towards the first power source voltage to a second logic level when one of said first and second field effect transistors thereafter turn OFF; that said means includes a bipolar transistor (Q1, Q10) for pulling the potential at said second node towards the second power source voltage when said bipolar transistor is ON and a fourth load (Z4) for discharging a base charge of said bipolar transistor towards the first power source voltage when said bipolar transistor is OFF; that a detection signal indicative of a transition in the first and second address signal bits is obtained from said bipolar transistor and supplied to said first node; and that a transition detection signal indicative of a transition in at least one of the address signal bits is obtained from said first node (NNP).

Claim 12

An address transition detector circuit for detecting a transition of an address signal and for outputting a transition detection signal, said address transition detector circuit comprising a plurality of detection circuits (17 0 -17 n ) each supplied with two address signal bits which are both derived from the same bit of the address signal but have mutually different phases, first and second power sources (V oo , GND) respectively for generating first and second power source voltages, a first node (NNP) which connects outputs of said detection circuits, and a first load (R3) which is connected between said first power source and said first node, an arbitrary one of said detection circuits comprising a first gate circuit (10) having first and second input terminals for receiving a first address signal bit at the first input terminal, a second gate circuit (11) having third and fourth input terminals for receiving a second address signal bit at the third input terminal, said first and second address signal bits being derived from the same address signal bit but having mutually different phases, a second load (ZI) for feeding back an output signal of said first gate circuit to the fourth input terminal, a third load (Z2) for feeding back an output signai of said second gate circuit to the second input terminal, a third gate circuit (12, 13) supplied with the ouyput signals of said first and second gate circuits, said third gate circuit comprising first and second field effect transistors (12, 13) which are connected in series between second and third nodes, said output signal of said first gate circuit being supplied to a gate of said first field effect transistor and said output signal of said second gate circuit being supplied to a gate of said second field effect transistor so that said first and second field effect transistors are simultaneously turned ON for a predetermined time when said first and second address signals undergo a transition, characterized in that said arbitrary detection circuit is further provided with means (01, Q10, Z4) coupled to said first and second nodes and to said first and second power sources (V DD , GND) for pulling a potential at said second node towards the second power source voltage to a first logic level when both said first and second field effect transistors (12, 13) are turned ON and for pulling the potential at said second node towards the first power source voltage to a second logic level when one of said first and second field effect transistors thereafter turn OFF; that said means includes a bipolar transistor (Q1, Q10) for pulling the potential at said second node towards the second power source voltage when said bipolar transistor is ON and a fourth load (Z4) for discharging a base charge of said bipolar transistor towards the first power source voltage when said bipolar transistor is OFF; that a detection signal indicative of a transition in the first and second address signal bits is obtained from said bipolar transistor and supplied to said first node; and that a transition detection signal indicative of a transition in at least one of the address signal bits is obtained from said first node (NNP).

Claim 13

The address transition detector circuit as claimed in claim 8 , characterized in that said bipolar transistor (Q10) is a pnp type bipolar transistor (Q10) having a base connected to said second node, a collector coupled to said second power source (GND) and an emitter which is coupled to said first power source (V DD ) through said fourth load (Z4), said detection signal being obtained from a node which connects said fourth load and the emitter of said bipolar transistor.

Claim 14

The address transition detector circuit as claimed in any of claims 6 to 9, characterized in that there is further provided an inverter (18) for inverting the transition detection signal which is output from said first node (NNP).

Claim 15

The address transition detector circuit as claimed in claims 2, 4, 5, 7, 9 or 10, characterized in that said first and fourth loads (Z3, Z4) are resistors.

Claim 16

The address transition detector circuit as claimed in any of claims 1 to 11, characterized in that said second power source voltage (GND) is a ground potential.