Patent EP0368310A2 successfully refreshed from Google Patents.
EP0368310A2
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EP
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Nonvolatile memory device capable of outputting correct read data at proper time
Assignee: Toshiba Corp
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Filing: 1989-11-09
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Granted: —
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Expires: 2009-11-09
Abstract
Abstract A nonvolatile memory device has a memory cell (12) having its gate connected to a word line (WL), its source connected to a ground potential (Vss) and its drain connected to a power supply voltage (Vcc) via a bit line (BL) and a dummy cell (24) having its gate connected to the word line (WL), its source connected to the source potential and its drain connected to the power supply voltage (Vcc) via a dummy bit line (DBL). The bit line (BL) and the dummy bit line (DBL) are connected to reset and set terminals of a sense amplifier circuit (28) comprising a flip-flop circuit (30) and a latch type of sense amplifier (22). The conductance of the dummy cell (24) is made smaller than that of the memory cell (12) so that the speed at which the potential on the bit line (BL) is lowered depends on the state of injection of electrons into the memory cell (12) as compared with the speed at which the potential on the dummy bit line (DBL) at a time of reading data. The flip-flop circuit is reset or set in accordance with the speed at which (30) the potential on the bit line (BL) is lowered and then the latch type of sense amplifier (22) operates to latch the output of the flip-flop circuit (30) and output it as read data.
Inventors
- 👤 Yukio C/O Intellectual Prop. Div. Wada
- 👤 Tadashi C/O Intellectual Prop. Div. Maruyama
- 👤 Toshimasa C/O Intellectual Prop. Div. Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:25
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28; G11C7/00; G11C7/06; G11C7/065
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
220 words
A nonvolatile memory device comprising a first data read line having an end connected to a first power supply for providing a predetermined power supply voltage; first nonvolatile semiconductor means having a current path connected between said first data read line and a second power supply and a control electrode; a word line connected to said control electrode of said first nonvolatile semiconductor means; and sense amplifier circuit means having an input section connected to said first nonvolatile semiconductor means and an output section for outputting read data from said output section, characterized by further comprising a second data read line (DBL) having an end connected to said first power supply (Vcc) and second nonvolatile semiconductor means (24) having a current path connected between said second data read line (DBL) and said second power supply (Vss), characterized in that said word line (WL) is connected to said control electrode of said second nonvolatile semiconductor means (24), said sense amplifier circuit means (28) has an input section with first and second input sections connected to said first and second nonvolatile semiconductor means (12, 24), respectively, and an output section for outputting read data from said output section at a predetermined time according to potentials on said first and second read lines (BL, DBL) applied to said first and second input sections.
Claim 2
Dependent Claim
220 words
A nonvolatile memory device comprising a first data read line having an end connected to a first power supply for providing a predetermined power supply voltage; first nonvolatile semiconductor means having a current path connected between said first data read line and a second power supply and a control electrode; a word line connected to said control electrode of said first nonvolatile semiconductor means; and sense amplifier circuit means having an input section connected to said first nonvolatile semiconductor means and an output section for outputting read data from said output section, characterized by further comprising a second data read line (DBL) having an end connected to said first power supply (Vcc) and second nonvolatile semiconductor means (24) having a current path connected between said second data read line (DBL) and said second power supply (Vss), characterized in that said word line (WL) is connected to said control electrode of said second nonvolatile semiconductor means (24), said sense amplifier circuit means (28) has an input section with first and second input sections connected to said first and second nonvolatile semiconductor means (12, 24), respectively, and an output section for outputting read data from said output section at a predetermined time according to potentials on said first and second read lines (BL, DBL) applied to said first and second input sections.
Claim 3
Dependent Claim
76 words
A device according to claim 1, characterized in that said sense amplifier circuit means (28) comprises flip-flop circuit means (30) for outputting output data at a time according to the potentials on said first and second read lines (BL, DBL) applied to said first and second input sections and latch circuit means (22) for latching the output data of said flip-flop circuit means (30) for a predetermined time and then outputting it as the read data.
Claim 4
Dependent Claim
28 words
A device according to claim 1 or 2, characterized in that said first nonvolatile semiconductor means (12) has a larger conductance than said second nonvolatile semiconductor means (24).
Claim 5
Dependent Claim
87 words
A device according to claim 2, characterized in that said flip-flop circuit means (30) is set when the potential on said first read line (BL) applied to said input section arrives at a circuit threshold voltage faster than the potential on said second read line (DBL) and is reset the output data to said latch circuit when the potential on said second read line (DBL) applied to said second input section arrives at the circuit threshold voltage faster than the potential on said first read line (BL).
Claim 6
Dependent Claim
81 words
A device according to claim 4, characterized by further comprising a first load semiconductor element (32) having its current path connected between said first power supply (Vcc) and said first data read line (BL) and its control electrode connected to said second power supply (Vss) and a second load semiconductor element (34) having its current path connected between said first power supply (Vcc) and said second data read line (DBL) and its control electrode connected to said second power supply (Vss).
Claim 7
Dependent Claim
81 words
A device according to claim 4, characterized by further comprising a first load semiconductor element (32) having its current path connected between said first power supply (Vcc) and said first data read line (BL) and its control electrode connected to receive a predetermined clock signal and a second load semiconductor element (34) having its current path connected between said first power supply (Vcc) and said second data read line (DBL) and its control electrode connected to receive a predetermined pulse signal.
Claim 8
Dependent Claim
39 words
A device according to claim 6, characterized in that the pulse signals are applied to said control electrodes of said first and second load semiconductor elements (32, 34) only when said word line (WL) is at a high potential.
Claim 9
Dependent Claim
130 words
A device according to claim 4, characterized by further comprising a first load semiconductor element (32) having its current path connected between said first power supply (Vcc) and said first data read line (BL) and its control electrode connected to receive a predetermined pulse signal, a second load semiconductor element (34) having its current path connected between said first power supply (Vcc) and said second data read line (DBL) and its control electrode connected to receive a predetermined pulse signal and AND circuit means (36) having its first input terminal connected to said control electrode of said first load semiconductor element (32), its second input terminal connected to a word-line control line (WLC) adapted to control said word line (WL) and its output terminal connected to said word line (WL).
Claim 10
Dependent Claim
278 words
A nonvolatile memory device comprising a first data read line having an end connected to a first power supply for providing a predetermined power supply voltage; first nonvolatile semiconductor means having a current path connected between said first data read line and a predetermined write line and a control electrode; a word line connected to said control electrode of said first nonvolatile semiconductor means; and sense amplifier circuit means having an input section connected to said first nonvolatile semiconductor means and an output section for outputting read data from said output section, characterized by further comprising a second data read line (DBL) having an end connected to said first power supply (Vcc) and second nonvolatile semiconductor means (40) having a current path connected between said second data read line (DBL) and said second power supply (Vss), characterized in that said word line (WL) is connected to said control electrode of said second nonvolatile semiconductor means (40), said first nonvolatile semiconductor means (38) has the other end of its current path connected to said predetermined write line, said sense amplifier circuit means (28) has as said input section first and second input sections connected to said first and second nonvolatile semiconductor means (38, 40), respectively, and an output section for outputting read data from said output section at a predetermined time according to potentials on said first and second read lines (BL, DBL) applied to said first and second input sections, and said write line (WRL) is set to the same potential as that provided by said second power supply (Vss) at a time of reading data and set to a high potential at a time of writing data.
Claim 11
Dependent Claim
278 words
A nonvolatile memory device comprising a first data read line having an end connected to a first power supply for providing a predetermined power supply voltage; first nonvolatile semiconductor means having a current path connected between said first data read line and a predetermined write line and a control electrode; a word line connected to said control electrode of said first nonvolatile semiconductor means; and sense amplifier circuit means having an input section connected to said first nonvolatile semiconductor means and an output section for outputting read data from said output section, characterized by further comprising a second data read line (DBL) having an end connected to said first power supply (Vcc) and second nonvolatile semiconductor means (40) having a current path connected between said second data read line (DBL) and said second power supply (Vss), characterized in that said word line (WL) is connected to said control electrode of said second nonvolatile semiconductor means (40), said first nonvolatile semiconductor means (38) has the other end of its current path connected to said predetermined write line, said sense amplifier circuit means (28) has as said input section first and second input sections connected to said first and second nonvolatile semiconductor means (38, 40), respectively, and an output section for outputting read data from said output section at a predetermined time according to potentials on said first and second read lines (BL, DBL) applied to said first and second input sections, and said write line (WRL) is set to the same potential as that provided by said second power supply (Vss) at a time of reading data and set to a high potential at a time of writing data.
Claim 12
Dependent Claim
23 words
A device according to claim 9, characterized in that said first and second nonvolatile semiconductor means (38, 40) have a light-doped drain structure.
Claim 13
Dependent Claim
76 words
A device according to claim 10, characterized in that said sense amplifier circuit means (28) comprises flip-flop circuit means (30) for outputting output data at a time according to the potentials on said first and second read lines (BL, DBL) applied to said first and second input sections and latch circuit means (22) for latching the output data of said flip-flop circuit means (30) for a predetermined time and then outputting it as the read data.
Claim 14
Dependent Claim
26 words
A device according to claim 11, characterized in that said first nonvolatile semiconductor means (38) has a larger conductance than said second nonvolatile semiconductor means (40).
Claim 15
Dependent Claim
91 words
A device according to claim 12, characterized in that said flip-flop circuit means (30) is set when the potential on said first read line (BL) applied to said input section arrives at a circuit threshold voltage faster than the potential on said second read line (DBL) and is reset to output the output data to said latch circuit means (22) when the potential on said second read line (DBL) applied to said second input section arrives at the circuit threshold voltage faster than the potential on said first read line (BL).
References Cited (Backward Citations)
No citation records indexed.
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