Patent EP0368144A2 successfully refreshed from Google Patents.
EP0368144A2
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Digital computing system with low power mode
Assignee: Motorola Solutions Inc
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Filing: 1989-11-02
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Granted: —
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Expires: 2009-11-02
Abstract
Abstract An integrated circuit microcomputer (10) enters a low power mode in response to executing an LPSTOP instruction. Only reset events and those interrupt events having a priority level sufficiently high to pass an interrupt mask are capable of causing the termination of the low power mode. The LPSTOP instruction causes immediate data to be loaded into a status register, resetting the interrupt mask bits. The interrupt mask is then written, by means of a special bus cycle, into an interrupt mask register in a sub-system (16) within the microcomputer. This subsystem (16) then shuts down the clock signals to the remainder of the microcomputer (10), leaving only this sub-system (16) active. The active sub-system (16) performs a comparison of the priority levels of received interrupt requests to the interrupt mask during the low power mode.
Inventors
- 👤 Antone Louis Fourcroy
- 👤 Mark William Mcdermott
- 👤 John P. Dunn
- 👤 Bradley G. Burgess
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 15:37
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30083; G06F1/3203; G06F9/30145; G06F9/3016; G06F9/30167
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
152 words
A digital computing system (10) comprising: a central processing unit (11) operative in response to receipt of a clock signal and comprising: first means (21) for executing instructions; second means (20) for selectively responding to an interrupt request signal dependent on a result of a comparison between a priority level of the interrupt request signal and an interrupt mask; and register means (22) for storing the interrupt mask under control of the first means; a communication bus (12) coupled to the central processing unit (10); and clock signal generation logic (16) connected to the central processing unit to provide the clock signal thereto; wherein the improvement comprises: the first means (21) responds to a particular one of the instructions by placing signals representing the interrupt mask on the communication bus (12) and by causing the clock signal generation logic (16) to cease providing the clock signal to the central processing unit (11).
Claim 2
Dependent Claim
152 words
A digital computing system (10) comprising: a central processing unit (11) operative in response to receipt of a clock signal and comprising: first means (21) for executing instructions; second means (20) for selectively responding to an interrupt request signal dependent on a result of a comparison between a priority level of the interrupt request signal and an interrupt mask; and register means (22) for storing the interrupt mask under control of the first means; a communication bus (12) coupled to the central processing unit (10); and clock signal generation logic (16) connected to the central processing unit to provide the clock signal thereto; wherein the improvement comprises: the first means (21) responds to a particular one of the instructions by placing signals representing the interrupt mask on the communication bus (12) and by causing the clock signal generation logic (16) to cease providing the clock signal to the central processing unit (11).
Claim 3
Dependent Claim
143 words
A digital computing system (10) according to claim 1 wherein the improvement further comprises: first logic means (16) coupled to the communication bus for storing the signals representing the interrupt mask; second logic means (16) coupled to the first logic means and being active only if the clock signal generation logic is not providing the clock signal to the central processing unit for responding to an interrupt request signal by comparing a priority level of the interrupt request signal to the contents of the first logic means (16); third logic means (16) for selectively causing the clock signal generation logic to resume providing the clock signal to the central processing unit dependent on a result of the comparison performed by the second logic means; and the clock signal generation logic continuously provides a clock signal to the first, second and third logic means.
Claim 4
Dependent Claim
44 words
A digital computing system according to claim 2 wherein the improvement further comprises: the first means (21) further responds to the particular one of the instructions by storing in the register means (22) an immediate bit field of the particular one of the instructions.
Claim 5
Dependent Claim
207 words
An integrated circuit digital computing system (10) comprising an inter-module communication bus (12); a central processing unit (11) comprising: first interrupt mask means (22) for storing an interrupt mask; a bus controller (23) coupled to the inter-module communication bus (12); and first interrupt means (20) for selectively responding to an interrupt request received via the bus controller (23) from the inter-module communication bus (12) dependent on a comparison between a priority level of the interrupt request and the interrupt mask; and execution means (21) for executing instructions, the execution means is responsive to a particular instruction by causing the bus controller (23) to place predetermined signals and the interrupt mask on the inter-module communication bus (12); an integration module (16) coupled to the inter-module communication bus (12) comprising: second interrupt mask means (16) for storing, in response to the the receipt of the predetermined signals from the inter-module communication bus (12), the interrupt mask; and clock signal generation means (16) for providing, via the inter-module communication bus (12), a clock signal to the central processing unit and for ceasing to provide the clock signal to the central processing unit in response to the receipt of the predetermined signals and interrupt mask from the inter-module communication bus (12).
Claim 6
Dependent Claim
207 words
An integrated circuit digital computing system (10) comprising an inter-module communication bus (12); a central processing unit (11) comprising: first interrupt mask means (22) for storing an interrupt mask; a bus controller (23) coupled to the inter-module communication bus (12); and first interrupt means (20) for selectively responding to an interrupt request received via the bus controller (23) from the inter-module communication bus (12) dependent on a comparison between a priority level of the interrupt request and the interrupt mask; and execution means (21) for executing instructions, the execution means is responsive to a particular instruction by causing the bus controller (23) to place predetermined signals and the interrupt mask on the inter-module communication bus (12); an integration module (16) coupled to the inter-module communication bus (12) comprising: second interrupt mask means (16) for storing, in response to the the receipt of the predetermined signals from the inter-module communication bus (12), the interrupt mask; and clock signal generation means (16) for providing, via the inter-module communication bus (12), a clock signal to the central processing unit and for ceasing to provide the clock signal to the central processing unit in response to the receipt of the predetermined signals and interrupt mask from the inter-module communication bus (12).
Claim 7
Dependent Claim
78 words
An integrated circuit digital computing system (10) according to claim 4 wherein the integration module (16) further comprises: second interrupt means (16) for selectively responding to an interrupt request dependent on a comparison between a priority level of the interrupt request and the interrupt mask stored in the second interrupt mask means (16); and the clock signal generation means (16) is responsive to the second interrupt means to resume providing the clock signal to the central processing unit.
Claim 8
Dependent Claim
54 words
An integrated circuit digital computing system according to claim 4 wherein the integration module further comprises: means (16) for coupling the system to an external bus, the means for coupling being responsive to receipt of the predetermined signals and interrupt mask to place the predetermined signals and the interrupt mask on the external bus.
References Cited (Backward Citations)
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