Patent EP0367182A2 successfully refreshed from Google Patents.
EP0367182A2
Expired / Lapsed
EP
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High-speed digital computing system
Assignee: Philips GmbH
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Filing: 1989-10-30
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Granted: —
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Expires: 2009-10-30
Abstract
Abstract A high speed digital computing system and method including a plurality of subsystems each including a digital processing device, the subsystems being arranged in a ring. Parallel data transfer interconnections are provided between each subsystem. The plurality of subsystems are closely coupled by an interface residing on each subsystem which functions to transfer data packets onto, and receive data packets from, the ring formed by the subsystems. Each subsystem may include a powerful microprocessor and a programmable hardware booster. The interface structure and operation allows packets of data to be exchanged between the subsystems rapidly and without any deadlock occurring. The described embodiments have the significant advantages of providing high speed computation, expandable to any size required by the user, and configurable to make the most efficient use of the embodiment. One particular application of the present invention is in a computer system adapted for carrying out computer graphics image computation tasks.
Inventors
- 👤 Leland K. Putnam
- 👤 Philip H. Lucht
- 👤 Kenneth C. Johnson
- 👤 Scott K. Pritchett
- 👤 William Foster, Iii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 21:43
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17337; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015; G06T; G06T1/00; G06T1/20
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
252 words
A high-speed digital computing system comprising: a plurality of subsystem means for performing digital computation tasks; ring connection means for connecting said plurality of subsystem means into a ring wherein parallel data transfer connections run between each adjacent subsystem means in said ring; and wherein said subsystem means is each comprised of: processor means for digital processing of data received by said subsystem means; processor memory means, connected to said processor means, for storage of data to be utilized by said processor means, and for storage of data processed by said processor means; interface means for alternately inputting data to and receiving data from said ring of subsystem means, and for configuring said data as packets, each said interface means comprising an input storage means for temporary storage of said data packets as they are input on said ring to the interface means, and output buffer means for temporary storage of said data packets as they are transferred onto said ring, said output buffer means serving to limit the size of said data packets so they do not exceed the storage capacity of the input storage means so as to insure that no data packet can be output onto said ring where the output data packet is larger than the amount of storage capacity of any available input storage means on said ring; and wherein said input storage means of each interface means is connected by said ring connection means to an output buffer means of a preceding subsystem in said ring.
Claim 2
Dependent Claim
252 words
A high-speed digital computing system comprising: a plurality of subsystem means for performing digital computation tasks; ring connection means for connecting said plurality of subsystem means into a ring wherein parallel data transfer connections run between each adjacent subsystem means in said ring; and wherein said subsystem means is each comprised of: processor means for digital processing of data received by said subsystem means; processor memory means, connected to said processor means, for storage of data to be utilized by said processor means, and for storage of data processed by said processor means; interface means for alternately inputting data to and receiving data from said ring of subsystem means, and for configuring said data as packets, each said interface means comprising an input storage means for temporary storage of said data packets as they are input on said ring to the interface means, and output buffer means for temporary storage of said data packets as they are transferred onto said ring, said output buffer means serving to limit the size of said data packets so they do not exceed the storage capacity of the input storage means so as to insure that no data packet can be output onto said ring where the output data packet is larger than the amount of storage capacity of any available input storage means on said ring; and wherein said input storage means of each interface means is connected by said ring connection means to an output buffer means of a preceding subsystem in said ring.
Claim 3
Dependent Claim
71 words
A system as defined in claim 1 wherein each said interface means further comprises input control means, connected to said input storage means, for identifying when a data packet is addressed to the subsystem means of that interface means, and for controlling data transfer from said input storage means to said processor means of that subsystem means, or to an adjacent input storage means of another subsystem means in said ring.
Claim 4
Dependent Claim
68 words
A system as defined in claim 1 wherein each said interface means further comprises means for monitoring each data packet which it outputs onto said ring, so that if a data packet travels around the ring more than a predetermined number of times without having been received by another subsystem means to which said data packet was sent, then said data packet may be removed from the ring.
Claim 5
Dependent Claim
249 words
A high-speed digital computing system comprising: an external computer; a plurality of digital processing subsystems for performing digital computation tasks, at least one of said subsystems comprising a controller means, connected to said external computer, for controlling data transfer between said external computer and the other subsystems, each said subsystem comprising digital processor means for performing said digital computation tasks, and processor memory means, connected to said processor means, for storage of data to be utilized by said processor means, and for storage of data processed by said processor means, and wherein each said subsystem is connected by a parallel data transfer bus between adjacent subsystems so as to form a continuous ring of said subsystems; and for each said subsystem, an interface means for outputting data onto and receiving data from said ring, and for configuring said data as packets, each said interface means comprising: an input storage means for receiving data packets from an adjacent, preceding subsystem; an output buffer means for transferring data packets to an adjacent, following subsystem, said output buffer means being connected to the input storage means of said following subsystem; and wherein said output buffer means and said input storage means of each said subsystem are sized in terms of their storage capacity with respect to each other such that data packets output by an output buffer means onto said ring will not exceed the storage capacity of the input storage means of the subsystem from which said data packet is output.
Claim 6
Dependent Claim
249 words
A high-speed digital computing system comprising: an external computer; a plurality of digital processing subsystems for performing digital computation tasks, at least one of said subsystems comprising a controller means, connected to said external computer, for controlling data transfer between said external computer and the other subsystems, each said subsystem comprising digital processor means for performing said digital computation tasks, and processor memory means, connected to said processor means, for storage of data to be utilized by said processor means, and for storage of data processed by said processor means, and wherein each said subsystem is connected by a parallel data transfer bus between adjacent subsystems so as to form a continuous ring of said subsystems; and for each said subsystem, an interface means for outputting data onto and receiving data from said ring, and for configuring said data as packets, each said interface means comprising: an input storage means for receiving data packets from an adjacent, preceding subsystem; an output buffer means for transferring data packets to an adjacent, following subsystem, said output buffer means being connected to the input storage means of said following subsystem; and wherein said output buffer means and said input storage means of each said subsystem are sized in terms of their storage capacity with respect to each other such that data packets output by an output buffer means onto said ring will not exceed the storage capacity of the input storage means of the subsystem from which said data packet is output.
Claim 7
Dependent Claim
20 words
The system as defined in claim 1 or claim 4 wherein said parallel data transfer bus is 32 bits wide.
Claim 8
Dependent Claim
39 words
The system as defined in claim 1 or claim 4 wherein each said processor means comprises a microprocessor and wherein said subsystems each comprise a programmable hardware booster coupled to said microprocessor through a first-in first-out (FIFO) memory device.
Claim 9
Dependent Claim
31 words
The system as defined in claim 1 or claim 4 wherein said input storage means and said output buffer means of each said interface means comprise an identically sized storage capacity.
Claim 10
Dependent Claim
43 words
The system as defined in claim 7 wherein said input storage means comprises a first-in first-out (FIFO) memory device, and wherein said output buffer means comprises a digital memory device, and wherein each said device is 34 bits wide and 1024 words deep.
Claim 11
Dependent Claim
48 words
The system as defined in claim 1 or claim 4 wherein each said interface means further comprises output control means, connected to said output buffer means, for synchronizing the transfer of a data packet between said output buffer means and said input storage means of said following subsystem.
Claim 12
Dependent Claim
131 words
The system as defined in claim 9 wherein each said interface means further comprises means for communicating from said input storage means a status signal to said buffer means of said preceding subsystem from which a data packet is being sent, said status signal indicating when the input storage means is filled with data to a predetermined amount of its storage capacity, and wherein each said control means receives a status signal from an input storage means of an adjacent, following subsystem, said control means thereafter initiating a count so that if available storage capacity of the input storage means of the following subsystem does not increase before said count expires, then further data input to said input storage means of the following subsystem is temporarily halted by said control means.
Claim 13
Dependent Claim
18 words
The system as defined in claim 10 wherein said output control means comprises an output arbitration state machine.
Claim 14
Dependent Claim
25 words
The system as defined in claim 10 wherein said output control means further comprises an output word counter connected to said output arbitration state machine.
Claim 15
Dependent Claim
55 words
The system as defined in claim 12 wherein each said interface means further comprises a first latch connected to the input of said output word counter, a second latch connected to said output buffer means on an input side thereof, and a third latch connected to said output buffer means on an output side thereof.
Claim 16
Dependent Claim
36 words
The system as defined in claim 11 wherein said output control means further comprises a counter connected to said output arbitration state machine, said counter comprising means for receiving said status signal which initiates said count.
Claim 17
Dependent Claim
79 words
The system as defined in claim 4 wherein each said interface means further comprises means for monitoring each data packet which is output by the subsystem of that interface means onto said ring, so that if a data packet returns to the subsystem from which it was sent more than a predetermined number of times without having been received by another subsystem to which said data packet was sent, then the data packet may be removed from the ring.
Claim 18
Dependent Claim
71 words
The system as defined in claim 4 wherein each said interface means further comprises input control means, connected to said input storage means, for identifying when a data packet is addressed to the subsystem of that interface means, and for controlling data transfer from said input storage means to the addressed processor means of that subsystem or to a following subsystem if the addressed processor means of that subsystem is busy.
Claim 19
Dependent Claim
18 words
The system as defined in claim 16 wherein said input control means comprises an input arbitration state machine.
Claim 20
Dependent Claim
66 words
The system as defined in claim 17 wherein said input control means further comprises an input word counter connected on an output side of said input storage means and connected on an input side of said input arbitration state machine, and an input buffer connected on said output side of said input storage means and connected on said input side of said input arbitration state machine.
Claim 21
Dependent Claim
251 words
An interface for providing parallel transfer data connections between a plurality of processors each containing one such interface, said processors being connected one to another to form a ring wherein packets of data may be transferred around the ring from one processor to another, said interface comprising: input storage means for temporary storage of said data packets as they are input to one processor from another processor of said ring; output buffer means for temporary storage of said data packets as they are transferred from one processor of said ring to the next, said output buffer having a storage capacity sized so as to limit the size of a data packet output therefrom such that no data packet can be output onto said ring where the output data packet is larger than the amount of storage capacity of any available input storage means of the processors on said ring; input control means, connected to said input storage means, for identifying whether data packet is addressed to the processor receiving the data packet at its input storage means, and if so, thereafter transferring the data packet to the addressed processor and permitting asynchronous processing of the data packet relative to other processors in the ring, and if not, preparing the data packet for transfer to the next processor in the ring; and output control means, connected to said output buffer means, for synchronously transferring data packets from the output buffer means of one processor to the input storage means of the next.
Claim 22
Dependent Claim
251 words
An interface for providing parallel transfer data connections between a plurality of processors each containing one such interface, said processors being connected one to another to form a ring wherein packets of data may be transferred around the ring from one processor to another, said interface comprising: input storage means for temporary storage of said data packets as they are input to one processor from another processor of said ring; output buffer means for temporary storage of said data packets as they are transferred from one processor of said ring to the next, said output buffer having a storage capacity sized so as to limit the size of a data packet output therefrom such that no data packet can be output onto said ring where the output data packet is larger than the amount of storage capacity of any available input storage means of the processors on said ring; input control means, connected to said input storage means, for identifying whether data packet is addressed to the processor receiving the data packet at its input storage means, and if so, thereafter transferring the data packet to the addressed processor and permitting asynchronous processing of the data packet relative to other processors in the ring, and if not, preparing the data packet for transfer to the next processor in the ring; and output control means, connected to said output buffer means, for synchronously transferring data packets from the output buffer means of one processor to the input storage means of the next.
Claim 23
Dependent Claim
68 words
An interface as defined in claim 19 further comprising means for monitoring each data packet output onto said ring, so that if a data packet returns to the processor from which it was sent more than a predetermined number of times without having been received by another processor on the ring to which said data packet was sent, then said data packet may be removed from the ring.
Claim 24
Dependent Claim
129 words
An interface as defined in claim 20 further comprising means for communicating from said input storage means a status signal to the output buffer means from which a data packet is being sent to said input storage means, said status signal indicating when the input storage means is filled with data to a predetermined amount of its storage capacity, and wherein each said output control means comprises means for receiving a status signal from an input storage means so that as one processor transfers a data packet to the next processor in the ring, if available storage capacity of the input storage means of said next processor is less than said predetermined amount then further data input to said next processor is temporarily halted by said output control means.
Claim 25
Dependent Claim
19 words
An interface as defined in claim 19 wherein said input storage means comprises a first-in first-out (FIFO) memory device.
Claim 26
Dependent Claim
22 words
An interface as defined in claim 22 wherein said input storage means and said output buffer means have identically sized storage capacities.
Claim 27
Dependent Claim
37 words
An interface as defined in claim 19 wherein said output control means comprises an output arbitration state machine and wherein said output control means further comprises an output word counter connected to said output arbitration state machine.
Claim 28
Dependent Claim
50 words
An interface as defined in claim 24 further comprising a first latch connected to the output of said output word counter, a second latch connected to said output buffer means on an input side thereof, and a third latch connected to said output buffer means on a output side thereof.
Claim 29
Dependent Claim
78 words
An interface as defined in claim 19 wherein said input control means comprises an input arbitration state machine and wherein said input control means further comprises an input word counter connected on an output side of said input storage means and connected on an input side of said input arbitration state machine, and an input buffer connected on said output side of said input storage means and connected on said input side of said input arbitration state machine.
Claim 30
Independent Claim
149 words
A method of distributing digital information among a plurality of processors in a digital computing system comprising a plurality of memory buffers connected to one another to form a ring digital communication path, the method comprising the steps of: outputting a first packet of digital information from a first processor onto the ring communication path, the first packet including a first destination address; limiting the size of the first packet such that the entire first packet may be stored in any one of the memory buffers; comparing the destination address of the first packet with the address of a second processor; and passing the first packet past the second processor if the destination address of the first packet does not match the second processor address; and inputting the first packet into the second processor if the destination address of the first packet matches the address of the second processor.
Claim 31
Independent Claim
149 words
A method of distributing digital information among a plurality of processors in a digital computing system comprising a plurality of memory buffers connected to one another to form a ring digital communication path, the method comprising the steps of: outputting a first packet of digital information from a first processor onto the ring communication path, the first packet including a first destination address; limiting the size of the first packet such that the entire first packet may be stored in any one of the memory buffers; comparing the destination address of the first packet with the address of a second processor; and passing the first packet past the second processor if the destination address of the first packet does not match the second processor address; and inputting the first packet into the second processor if the destination address of the first packet matches the address of the second processor.
Claim 32
Dependent Claim
63 words
A method of distributing digital information among a plurality of processors as defined in claim 27 further comprising the step of transmitting a synchronization strobe signal from the first processor to the second processor to accompany the pass-through of the first packet and synchronize the transfer of the packet between the first processor and the second processor on the ring digital communication path.
Claim 33
Dependent Claim
70 words
A method of distributing digital information among a plurality of processors as defined in claim 27 wherein the first packet includes a trip count word, the method further comprising the step of decrementing the trip count word as the packet passes by the second processor and the step of removing the packet from the ring digital communication path when the trip count word has been decremented to a given value.
Claim 34
Dependent Claim
59 words
A method of distributing digital information among a plurality of processors as defined in claim 27 wherein the step of outputting a first packet from a first processor onto the ring communication path comprises the steps of: halting pass through of any other packets on the ring communication path; and inserting the first packet onto the ring communication path.
References Cited (Backward Citations)
No citation records indexed.
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