Patent US2020221A successfully refreshed from Google Patents.
Patent EP0366343A2 successfully refreshed from Google Patents.
EP0366343A2
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EP
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Integrated circuit fabrication, including low temperature method for making silicide structures
Assignee: AT&T Inc
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Filing: 1989-10-18
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Granted: —
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Expires: 2009-10-18
Abstract
Abstract In a method of semiconductor integrated circuit fabrication, use of boron and phosphorus doped TEOS (i.e., BPTEOS) as a first-level dielectric permits the dielectric to be flowed at a maximum temperature of 800<o>C. Consequently, TiSi2 source and drain contacts may be used in a field effect transistor without suffering nucleation and consequent increase in grain size, as well as increased resistivity. A layer of TEOS may be deposited before the layer of BPTEOS to prevent sharp corners on the gate from causing thinning and possible breakdown of the BPTEOS layer.
Inventors
- 👤 Min-Liang Chen
- 👤 Chung Wai Leung
- 👤 Edward P. Martin, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 09:41
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/6923; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10W; H10W20/00; H10W20/01; H10W20/071
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
64 words
A method of semiconductor integrated circuit fabrication comprising the steps of: forming silicide source , gate , and drain regions of a field effect transistor; depositing a first dielectric layer over said silicide regions; flowing said dielectric layer, CHARACTERIZED IN THAT said dielectric layer is formed by depositing BPTEOS having boron and phosphorus each present in amounts ranging from 3.5 to 4.5 weight percent.
Claim 2
Independent Claim
64 words
A method of semiconductor integrated circuit fabrication comprising the steps of: forming silicide source , gate , and drain regions of a field effect transistor; depositing a first dielectric layer over said silicide regions; flowing said dielectric layer, CHARACTERIZED IN THAT said dielectric layer is formed by depositing BPTEOS having boron and phosphorus each present in amounts ranging from 3.5 to 4.5 weight percent.
Claim 3
Dependent Claim
25 words
A method as recited in claim 1 further CHARACTERIZED IN THAT said flowing occurs at a temperature of approximately 800 o C 50 o C.
Claim 4
Dependent Claim
16 words
A method as recited in claim 1 in which said silicide regions consist essentially of TiSi₂.
Claim 5
Dependent Claim
18 words
A method as recited in claim 1 in which said silicide regions are formed by a self-aligning process.
Claim 6
Dependent Claim
38 words
A method, as recited in claim 1, further including the step of depositing a second dielectric layer over said silicide region prior to deposition of said first dielectric layer, said second dielectric layer being formed by depositing TEOS.
Claim 7
Independent Claim
79 words
A method of integrated circuit fabrication comprising the steps of: forming silicide source, gate, and drain regions of a field-effect transistor; depositing a dielectric layer over said silicide regions; heating said layer, CHARACTERIZED IN THAT said dielectric layer is formed by depositing a first layer of undoped dielectric and a second layer of doped dielectric upon said first layer of undoped dielectric, said second layer of doped dielectric including boron and phosphorous each of at least one percent weight.
Claim 8
Independent Claim
79 words
A method of integrated circuit fabrication comprising the steps of: forming silicide source, gate, and drain regions of a field-effect transistor; depositing a dielectric layer over said silicide regions; heating said layer, CHARACTERIZED IN THAT said dielectric layer is formed by depositing a first layer of undoped dielectric and a second layer of doped dielectric upon said first layer of undoped dielectric, said second layer of doped dielectric including boron and phosphorous each of at least one percent weight.
Claim 9
Independent Claim
118 words
A method of integrated circuit fabrication comprising the steps of: forming titanium salicide source, gate, and drain regions of a field effect transistor; depositing a first dielectric layer over said titanium salicide regions, said dielectric layer being formed from TEOS and having a thickness between 1500Å and 2500Å; depositing a second dielectric layer over said first dielectric layer, said second dielectric layer being formed from BPTEOS, having boron and phosphorus present in amounts of approximately 4 weight percent, said second dielectric layer having thickness between 3000Å and 4000Å; flowing said second dielectric layer by heating it to a temperature of approximately 800 o C in an atmosphere consisting essentially of nitrogen for between one half and two hours.
Claim 10
Independent Claim
118 words
A method of integrated circuit fabrication comprising the steps of: forming titanium salicide source, gate, and drain regions of a field effect transistor; depositing a first dielectric layer over said titanium salicide regions, said dielectric layer being formed from TEOS and having a thickness between 1500Å and 2500Å; depositing a second dielectric layer over said first dielectric layer, said second dielectric layer being formed from BPTEOS, having boron and phosphorus present in amounts of approximately 4 weight percent, said second dielectric layer having thickness between 3000Å and 4000Å; flowing said second dielectric layer by heating it to a temperature of approximately 800 o C in an atmosphere consisting essentially of nitrogen for between one half and two hours.
Claim 11
Dependent Claim
57 words
A semiconductor device comprising: a silicon substrate; silicide source, gate, and drain regions formed on said substrate; a first dielectric layer covering said silicide regions, said first dielectric layer being CHARACTERIZED IN THAT it is formed by the deposition of BPTEOS which has boron and phosphorous each present in amounts ranging from 3.5 to 4.5 weight percent.
Claim 12
Dependent Claim
57 words
A semiconductor device comprising: a silicon substrate; silicide source, gate, and drain regions formed on said substrate; a first dielectric layer covering said silicide regions, said first dielectric layer being CHARACTERIZED IN THAT it is formed by the deposition of BPTEOS which has boron and phosphorous each present in amounts ranging from 3.5 to 4.5 weight percent.
Claim 13
Dependent Claim
31 words
The device of claim 8 further including a second dielectric layer between said silicide regions and said first dielectric layer, said second dielectric layer being formed by the deposition of TEOS.
Claim 14
Dependent Claim
60 words
A semiconductor device comprising: a semiconductor substrate source and drain regions within said substrate, said source and drain regions having conductive, dopant-diffusion-resistant contacts; a gate overlying said substrate and between said source and drain regions; a first layer of undoped dielectric covering said gate; a second layer of doped dielectric at least partially covering said first layer of undoped dielectric.
Claim 15
Dependent Claim
60 words
A semiconductor device comprising: a semiconductor substrate source and drain regions within said substrate, said source and drain regions having conductive, dopant-diffusion-resistant contacts; a gate overlying said substrate and between said source and drain regions; a first layer of undoped dielectric covering said gate; a second layer of doped dielectric at least partially covering said first layer of undoped dielectric.
Claim 16
Dependent Claim
23 words
The device of claim 10 further including a spacer adjacent said gate, said spacer being covered by said first layer of undoped dielectric.
Claim 17
Dependent Claim
23 words
The device of claim 10 wherein said second dielectric layer has been flowed at 800 o C for at least one half hour.
Claim 18
Dependent Claim
22 words
The device of claim 10 wherein said second layer of dielectric contains boron and phosphorous each present in 4 1/2 weight percent.
Claim 19
Dependent Claim
17 words
The device of claim 10 wherein said first dielectric layer has a thickness of at least 1000Å.
Claim 20
Dependent Claim
29 words
The device of claim 10 wherein said second layer of doped dielectric has a dopant which promotes flow present in an amount of at least one percent by weight.
Claim 21
Dependent Claim
11 words
The device of claim 10 wherein said contacts are silicide regions.
References Cited (Backward Citations)
No citation records indexed.
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