Patent US2530458A successfully refreshed from Google Patents.
Patent US1600276A successfully refreshed from Google Patents.
Patent EP0364769A2 successfully refreshed from Google Patents.
EP0364769A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor device having a gate electrode consisting of a plurality of layers
Assignee: Toshiba Corp
•
Filing: 1989-09-26
•
Granted: —
•
Expires: 2009-09-26
Abstract
Abstract Disclosed is a semiconductor device having a gate electrode consisting of a plurality of layers. The semiconductor device comprises a substrate (21), a first diffusion layer (27) formed in the substrate, a second diffusion layer (207) formed in the substrate, a floating gate electrode (32) formed on a channel region between the first diffusion layer (27) and the second diffusion layer (207), and a control gate electrode (31) formed on the floating gate electrode (32) with an insulating film (25, 26) interposed therebetween. The first diffusion layer (27) and second diffusion layer (207) extend in parallel with each other along the longer side of the floating gate electrode (32). The control gate electrode (31) extends in parallel with the shorter side of the floating gate electrode (32). The wiring layers for the first diffusion layer (27) and second diffusion layer (207) extend across the wiring layer for the control gate electrode (31). Further, that portion of the first diffusion layer (27) which is positioned adjacent to the floating gate electrode (32) differs in impurity concentration from that portion of the second diffusion layer (207) which is positioned adjacent to the floating gate electrode (32).
Inventors
- 👤 Kuniyoshi Intellectual Property Div. Yoshikawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 06:46
CPC Classifications
H; H10; H10B; H10B69/00; H10B41/00; H10B41/30; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10P; H10P32/00; H10P32/10; H10P32/14
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
198 words
A semiconductor device having a gate electrode consisting of a plurality of layers, comprising: a semiconductor substrate (21); a first diffusion layer (27) formed in the substrate; a second diffusion layer (207) formed in the substrate; a floating gate electrode (32) formed in an electrically floating state on a channel region between the first diffusion layer (27) and the second diffusion layer (207); and a control gate electrode (31) formed on the floating gate electrode (32) with an insulating film (25, 26; 251, 26, 252) interposed therebetween; characterized in that the first diffusion layer (27) and the second diffusion layer (207) are formed in parallel with the longer side of the floating gate electrode (32); the control gate electrode (31) is formed in parallel with the shorter side of floating gate electrode (32); the first diffusion layer (27) and the second diffusion layer (207) extend across the control gate electrode (31); and the impurity concentration in that part of the first diffusion layer (27) which is positioned adjacent to the floating gate electrode (32) differs from the impurity concentration in that part of the second diffusion layer (207) which is positioned adjacent to the floating gate electrode (32).
Claim 2
Dependent Claim
198 words
A semiconductor device having a gate electrode consisting of a plurality of layers, comprising: a semiconductor substrate (21); a first diffusion layer (27) formed in the substrate; a second diffusion layer (207) formed in the substrate; a floating gate electrode (32) formed in an electrically floating state on a channel region between the first diffusion layer (27) and the second diffusion layer (207); and a control gate electrode (31) formed on the floating gate electrode (32) with an insulating film (25, 26; 251, 26, 252) interposed therebetween; characterized in that the first diffusion layer (27) and the second diffusion layer (207) are formed in parallel with the longer side of the floating gate electrode (32); the control gate electrode (31) is formed in parallel with the shorter side of floating gate electrode (32); the first diffusion layer (27) and the second diffusion layer (207) extend across the control gate electrode (31); and the impurity concentration in that part of the first diffusion layer (27) which is positioned adjacent to the floating gate electrode (32) differs from the impurity concentration in that part of the second diffusion layer (207) which is positioned adjacent to the floating gate electrode (32).
Claim 3
Dependent Claim
43 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 1, characterized in that the length in the longer side of the floating gate electrode (32) is equal to the width of the control gate electrode (31).
Claim 4
Dependent Claim
39 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 1, characterized in that the part of the first diffusion layer (27) which is positioned adjacent to the floating gate electrode contains arsenic.
Claim 5
Dependent Claim
39 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 1, characterized in that the part of the second diffusion layer (207) which is positioned adjacent to the floating gate electrode contains phosphorus.
Claim 6
Dependent Claim
43 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 1, characterized in that the upper surface of each of the first diffusion layer (27) and the second diffusion layer (28) is formed of a silicide layer.
Claim 7
Dependent Claim
61 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 1, characterized in that the insulating film interposed between the first diffusion layer (27), the second diffusion layer (207) and the control gate electrode (31) includes a thermal oxide film prepared by thermally oxidizing the first diffusion layer (27) and the second diffusion layer (207).
Claim 8
Dependent Claim
54 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim1, characterized in that the insulating film (30) formed on the silicide layer (29) covering the first diffusion layer (27) and the second diffusion layer (207) consists of an oxide film having a thickness of 1500 Å or more.
Claim 9
Dependent Claim
31 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 1, characterized in that the floating gate electrode (32) is formed of a polysilicon layer.
Claim 10
Dependent Claim
31 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 1, characterized in that the control gate electrode (31) is formed of a polysilicon layer.
Claim 11
Dependent Claim
73 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 1, characterized in that the impurity concentration in that part of the second diffusion layer (207) which is positioned adjacent to the floating gate electrode (32) is one ot two orders of magnitude lower than the impurity concentration in that part of the first diffusion laye (27) which is positioned adjacent to the floating gate electrode (32).
Claim 12
Dependent Claim
40 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 1, characterized in that the control gate electrode (31) is formed of a stacked structure consisting of a polysilicon layer and a silicide layer.
Claim 13
Dependent Claim
42 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 1, characterized in that the insulating film (25, 26) formed on the floating gate electrode (32) includes an oxide film prepared by oxidizing a polysilicon layer.
Claim 14
Dependent Claim
48 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 1, characterized in that the insulating film (25, 26) formed on the floating gate electrode (32) is of a stacked structure consisting of a silicon oxide film and a silicon nitride film.
Claim 15
Dependent Claim
58 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 1, characterized in that the insulating film (251, 26, 252) formed on the floating gate electrode (32) is of a stacked structure consisting of an oxide film prepared by oxidizing a polysilicon film, a silicon nitride film and a silicon oxide film.
Claim 16
Dependent Claim
67 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 1, characterized in that the impurity concentration in that part of the second diffusion layer (207) which is positioned adjacent to the floating gate electrode (32) is lower than the impurity concentration in that part of the first diffusion layer (27) which is positioned adjacent to the floating gate electrode (32).
Claim 17
Dependent Claim
47 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 15, characterized in that the first diffusion layer (27) acts as the drain and the second diffusion layer (207) acts as the source when the device performs the information writing function.
Claim 18
Dependent Claim
47 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 15, characterized in that the first diffusion layer (27) acts as the source and the second diffusion layer (207) acts as the drain when the device performs the information reading function.
Claim 19
Dependent Claim
61 words
The semiconductor device having a gate electrode consisting of a plurality of layers according to claim 15, characterized in that the part of the second diffusion layer (207) which is positioned adjacent to the floating gate electrode (32) and has a lower impurity concentration is located 0.7 micron or less apart from the floating gate electrode (32) in the vertical direction.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.