Patent EP0364393A2 successfully refreshed from Google Patents.
EP0364393A2
Expired / Lapsed
EP
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Power semiconductor device
Assignee: NTT Inc
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Filing: 1989-10-11
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Granted: —
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Expires: 2009-10-11
Abstract
Abstract A power semiconductor device includes a layered first insulating region (101) formed on a first major surface of a semiconductor layer (58), a first conductive layer (104, 105, 106, 107, 108, 109) formed on the first insulating region and having the same conductivity type as that of the semiconductor layer, a layered second insulating region (100) formed on the first conductive layer, a vertical power transistor (A) having the semiconductor layer as one of its components and formed on the first major surface of the semiconductor layer, a third insulating region (102) for dielectrically isolating the first conductive layer from the other conductive layer, and a control MIS transistor (B, C), formed on the second insulating region, for controlling the vertical power transistor. A predetermined bias is applied on the first conductive layer to prevent formation of a back channel of the control MIS transistor.
Inventors
- 👤 Terukazu Ohno
- 👤 Katutoshi Izumi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:32
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6733; H10D30/6734; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/80; H10D84/82; H10D84/83; H10D88/00; H10D88/01
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
146 words
A power semiconductor device comprising: a layered first insulating region (101) formed on a first major surface of a semiconductor layer (58); a first conductive layer (104, 105, 106, 107, 108, 109) formed on said first insulating region and having the same conductivity type as that of said semiconductor layer; a layered second insulating region (100) formed on said first conductive layer; a vertical power transistor (A) having said semiconductor layer as one of its components and formed on the first major surface of said semiconductor layer; a third insulating region (102) for dielectrically isolating said first conductive layer from the other conductive layer; and a control MIS transistor (B, C), formed on said second insulating region, for controlling said vertical power transistor, wherein a predetermined bias is applied on said first conductive layer to prevent formation of a back channel of said control MIS transistor.
Claim 2
Dependent Claim
146 words
A power semiconductor device comprising: a layered first insulating region (101) formed on a first major surface of a semiconductor layer (58); a first conductive layer (104, 105, 106, 107, 108, 109) formed on said first insulating region and having the same conductivity type as that of said semiconductor layer; a layered second insulating region (100) formed on said first conductive layer; a vertical power transistor (A) having said semiconductor layer as one of its components and formed on the first major surface of said semiconductor layer; a third insulating region (102) for dielectrically isolating said first conductive layer from the other conductive layer; and a control MIS transistor (B, C), formed on said second insulating region, for controlling said vertical power transistor, wherein a predetermined bias is applied on said first conductive layer to prevent formation of a back channel of said control MIS transistor.
Claim 3
Dependent Claim
23 words
A device according to claim 1, wherein said semiconductor layer (58) is formed on a semiconductor substrate (57) having the same conductivity type.
Claim 4
Dependent Claim
23 words
A device according to claim 1, wherein said semiconductor layer (58) is formed on a semiconductor substrate (120) having a different conductivity type.
Claim 5
Dependent Claim
40 words
A device according to claim 1, wherein said first conductive layer is connected to one of components constituting said control MIS transistor formed immediately above said first conductive layer via said second insulating region and is supplied with a bias.
Claim 6
Dependent Claim
23 words
A device according to claim 4, wherein a source (66, 81, 89) of said control transistor is connected to said first conductive layer.
Claim 7
Dependent Claim
60 words
A device according to claim 1, wherein said control transistor comprises a first complementary MIS inverter (B) constituted by a first n-channel MIS transistor and a first p-channel MIS transistor formed on the upper surface of said second insulating region, a source of said first n-channel MIS transistor being connected to and applying a bias on said first conductive layer.
Claim 8
Dependent Claim
35 words
A device according to claim 1, wherein said first conductive layer is formed in a region corresponding to a region of said control transistor arranged on said first conductive layer via said second insulating region.
Claim 9
Dependent Claim
15 words
A device according to claim 1, wherein said power transistor is a vertical MIS transistor.
Claim 10
Dependent Claim
25 words
A device according to claim 8, wherein a semiconductor layer arranged below said first insulating region is a drain region of said vertical MIS transistor.
Claim 11
Dependent Claim
145 words
A device according to claim 6, further comprising: second conductive layer and a third conductive layer formed on the upper surface of said first insulating region; a said second insulating region formed on the upper surfaces of said second and third conductive layers; another insulating region, formed between said second and third insulating regions, for dielectrically isolating said second and third conductive layers from each other and from the other conductive layer; and a second complementary MIS inverter (C) constituted by a second n-channel MIS transistor formed on said second conductive layer via said second insulating region and a second p-channel MIS transistor formed on said third conductive layer via said second insulating region, a source of said second n-channel MIS transistor being connected to said second conductive region, and a source of said second p-channel MIS transistor being connected to said third conductive layer.
Claim 12
Dependent Claim
34 words
A device according to claim 1, wherein said vertical power transistor is an n-p-n bipolar transistor, said semiconductor region located below said first insulating region being a collector region of said n-p-n bipolar transistor.
Claim 13
Dependent Claim
33 words
A device according to claim 1, wherein said power transistor is an IGBT (Insulated Gate Bipolar Transistor), said semiconductor layer located below said first insulating region being a drift region of said IGBT.
Claim 14
Dependent Claim
17 words
A device according to claim 1, wherein said control MIS transistor is a lateral type MIS transistor.
References Cited (Backward Citations)
No citation records indexed.
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