Patent EP0363882A2 successfully refreshed from Google Patents.
EP0363882A2
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EP
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Multiprocessor system using communication register having processor-associated storage locations
Assignee: NEC Corp
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Filing: 1989-10-09
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Granted: —
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Expires: 2009-10-09
Abstract
Abstract In a multiprocessor system, a communication register is partitioned into groups of word storage locations and one of the groups is further partitioned into subgroups associated respectively with the processors. An access controller accesses any groups of the communication register when a system program is being processed and accesses one of the subgroups when a user program is being processed. A write controller is responsive to a test & set instruction of first occurrence from a common bus for assembling a lock word with a data word, a control field and a counter field containing a variable count. The control field of the lock word is set to a first binary state when it is assembled and reset to a second binary state when deassembled. In response to a load instruction from the common bus, either the data word from the bus or lock word is stored into a specified storage area of a communication register. A read controller reads contents of an addressed location of the communication register onto the common bus in response to a save instruction. Test & set instruction of a subsequent occurrence causes the variable count in the stored lock word to be decremented as long as the control field remains set to the first binary state. When the count reduces to zero, a signal is applied to the common bus indicating the occurrence of a dead lock.
Inventors
- 👤 Hideo Hayashi
- 👤 Atsuo Mochizuki
- 👤 Ryuji Kobayashi
- 👤 Chiaki Kumamoto
- 👤 Reiko Kokubu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 08:46
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/167; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F9/00; G06F9/06; G06F9/46; G06F9/52; G06F9/526; G06F2209/00; G06F2209/52; G06F2209/521
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
305 words
A multiprocessor system having a plurality of processors connected to a common bus, means for granting permission to one of said processors to access said common bus, and a main memory connected to said common bus for storing data to be exchanged between said processors, comprising: a communication register connected to said common bus, said communication register being partitioned into a plurality of groups of word storage locations, one of said groups being further partitioned into a plurality of subgroups associated respectively with said processors; first access control means for accessing one of the word storage locations of said first and second groups of said communication register in accordance with a first address code of longer bit length supplied from said common bus when the granted processor is operating in a first mode; a plurality of directories associated respectively with said subgroups, each of said directories having a plurality of bit positions associated respectively with said processors; second access control means for accessing one of the word storage locations of one of said subgroups in accordance with a second address code of shorter bit length supplied from said common bus and contents of the bit positions of said directories when the granted processor is operating in a second mode; write control means for writing a data word of longer bit length from said common bus into a word storage location of the communication register either specified by the first or second access control means, forming a lock word with a data word of shorter bit length from said bus and writing the lock word into the specified word storage location of the communication register; and read control means for reading contents of a word storage location of said communication register specified by either of said first and second access control means onto said common bus.
Claim 2
Dependent Claim
305 words
A multiprocessor system having a plurality of processors connected to a common bus, means for granting permission to one of said processors to access said common bus, and a main memory connected to said common bus for storing data to be exchanged between said processors, comprising: a communication register connected to said common bus, said communication register being partitioned into a plurality of groups of word storage locations, one of said groups being further partitioned into a plurality of subgroups associated respectively with said processors; first access control means for accessing one of the word storage locations of said first and second groups of said communication register in accordance with a first address code of longer bit length supplied from said common bus when the granted processor is operating in a first mode; a plurality of directories associated respectively with said subgroups, each of said directories having a plurality of bit positions associated respectively with said processors; second access control means for accessing one of the word storage locations of one of said subgroups in accordance with a second address code of shorter bit length supplied from said common bus and contents of the bit positions of said directories when the granted processor is operating in a second mode; write control means for writing a data word of longer bit length from said common bus into a word storage location of the communication register either specified by the first or second access control means, forming a lock word with a data word of shorter bit length from said bus and writing the lock word into the specified word storage location of the communication register; and read control means for reading contents of a word storage location of said communication register specified by either of said first and second access control means onto said common bus.
Claim 3
Dependent Claim
48 words
A multiprocessor system as claimed in claim 1, further comprising multitasking control means for rewriting the contents of said directories in accordance with a directory control instruction from said granted processor when same is performing a multitasking operation with a master processor indicated by said directory control information.
Claim 4
Dependent Claim
105 words
A multiprocessor system as claimed in claim 2, wherein said directories are organized into a matrix of rows and columns, both of said rows and columns being respectively associated with said processors, the intersections of said rows and columns corresponding to the bit positions of said directories, wherein said multitasking control means rewrites the bit position of a directory at the intersection of the row and column which are associated with the granted processor, and rewrites the bit position of a directory at the intersection of the row which is associated with said master processor and the column which is associated with said granted processor.
Claim 5
Dependent Claim
192 words
A multiprocessor system as claimed in any one of claims 1 to 3, wherein said write control means is responsive to a test & set instruction of first occurrence from said common bus for assembling said lock word with said data word of shorter bit length, a control field and a counter field containing a variable count, said control field being set to a first binary state when said lock word is assembled and reset to a second binary state when said lock word is deassembled, said write control means being further responsive to a load instruction from said common bus for writing said lock word into a word storage area of said communication register specified by either of said first and second address control means; means responsive to the test & set instruction of a subsequent occurrence from said common bus for varying said variable count in the stored lock word by a predetermined amount when said control field remains set to said first binary state; and means for applying a signal to said common bus indicating the occurrence of an abnormal condition when said variable count attains a predetermined value.
Claim 6
Dependent Claim
257 words
A multiprocessor system as claimed in any one of claims 1 to 4, wherein said write control means comprises: input means connected to said common bus for receiving said data words of longer or shorter bit length; and a logic circuit responsive to said test & set instruction for storing a predetermined bit into a first bit position of said input means and all 1's into second bit positions of the input means, and responsive to said load instruction for loading the contents of said input means into a specified storage word location of said communication register, said input means containing said data word in third bit positions thereof, wherein said read control means comprises: output means connected to said communication register for receiving contents of a specified word storage location of said communication register in response to each of said test & set instruction and said save instruction, said output means having a first bit position connected to the first bit position of said input means, second bit positions connected to said varying means and third bit positions connected to the third bit positions of said input means, all bit positions of said output means being connected to said common bus, said logical circuit being responsive to the predetermined bit in said first bit position of said output means for rewriting the second bit positions of said input means with outputs of said varying means and rewriting the third bit positions of said input means with contents of the third bit positions of said output means.
Claim 7
Dependent Claim
280 words
A multiprocessor system having a plurality of processors connected to a common bus, means for granting permission to one of said processors to access said common bus, and a main memory connected to said common bus for storing data to be exchanged between said processors, comprising: a communication register connected to said common bus; access control means for accessing a specified storage area of said communication register in accordance with an address code supplied from said common bus; write control means responsive to a test & set instruction of first occurrence from said common bus for assembling a lock word with an exclusive data word supplied from said common bus, a control field and a counter field containing a variable count, said control field being set to a first binary state when said lock word is assembled and reset to a second binary state when said lock word is deassembled, said write control means being further responsive to a load instruction from said common bus for writing a non-exclusive data word from said bus and said lock word into a storage area of said communication register specified by said address control means; read control means for reading a word from said communication register onto said common bus in response to a save instruction therefrom; means responsive to the test & set instruction of a subsequent occurrence from said common bus for varying said variable count in the stored lock word by a predetermined amount when said control field remains set to said first binary state; and means for applying a signal to said common bus indicating the occurrence of an abnormal condition when said variable count attains a predetermined value.
Claim 8
Dependent Claim
280 words
A multiprocessor system having a plurality of processors connected to a common bus, means for granting permission to one of said processors to access said common bus, and a main memory connected to said common bus for storing data to be exchanged between said processors, comprising: a communication register connected to said common bus; access control means for accessing a specified storage area of said communication register in accordance with an address code supplied from said common bus; write control means responsive to a test & set instruction of first occurrence from said common bus for assembling a lock word with an exclusive data word supplied from said common bus, a control field and a counter field containing a variable count, said control field being set to a first binary state when said lock word is assembled and reset to a second binary state when said lock word is deassembled, said write control means being further responsive to a load instruction from said common bus for writing a non-exclusive data word from said bus and said lock word into a storage area of said communication register specified by said address control means; read control means for reading a word from said communication register onto said common bus in response to a save instruction therefrom; means responsive to the test & set instruction of a subsequent occurrence from said common bus for varying said variable count in the stored lock word by a predetermined amount when said control field remains set to said first binary state; and means for applying a signal to said common bus indicating the occurrence of an abnormal condition when said variable count attains a predetermined value.
Claim 9
Dependent Claim
95 words
A multiprocessor system as claimed in claim 6, wherein said communication register is partitioned into first and second groups of equal size and said second group is further partitioned into a plurality of equal subgroups respectively associated with said processors, wherein said processors operate in one of first and second modes, wherein said access control means accesses any of said first and second groups when the granted processor is operating in said first mode and accesses one of said subgroups which is associated with said granted processor when same is operating in said second mode.
Claim 10
Dependent Claim
77 words
A multiprocessor system as claimed in claim 7, wherein said access control means further comprises: a plurality of directories associated respectively with said subgroups, each of said directories having a plurality of bit positions associated respectively with said processors; and means for addressing one of said subgroups in accordance with an address code supplied from said granted processor and contents of the bit positions of said directories when the granted processor is operating in said second mode.
Claim 11
Dependent Claim
48 words
A multiprocessor system as claimed in claim 8, further comprising multitasking control means for rewriting the contents of said directories in accordance with a directory control instruction from said granted processor when same is performing a multitasking operation with a master processor indicated by said directory control information.
Claim 12
Dependent Claim
105 words
A multiprocessor system as claimed in claim 9, wherein said directories are organized into a matrix of rows and columns, both of said rows and columns being respectively associated with said processors, the intersections of said rows and columns corresponding to the bit positions of said directories, wherein said multitasking control means rewrites the bit position of a directory at the intersection of the row and column which are associated with the granted processor, and rewrites the bit position of a directory at the intersection of the row which is associated with said master processor and the column which is associated with said granted processor.
Claim 13
Dependent Claim
247 words
A multiprocessor system as claimed in any one of claims 6 to 10, wherein said write control means comprises: input means connected to said common bus and said communication register; and a logic circuit responsive to said test & set instruction for storing a predetermined bit into a first bit position of said input means and all 1's into second bit positions of the input means, and responsive to said load instruction for loading the contents of said input means into a specified area of said communication register, said input means storing said exclusive data word in third bit positions thereof, wherein said read control means comprises: output means connected to said communication register for receiving contents of a specified area of said communication register in response to either of said test & set instruction or said save instruction, said output means having a first bit position connected to the first bit position of said input means, second bit positions connected to said varying means and third bit positions connected to the third bit positions of said input means, all bit positions of said output means being connected to said common bus, said logical circuit being responsive to the predetermined bit in said first bit position of said output means for rewriting the second bit positions of said input means with outputs of said varying means and rewriting the third bit positions of said input means with contents of the third bit positions of said output means.
References Cited (Backward Citations)
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