Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
231 words
In a multiprocessor system comprising first through N-th instruction processing units where N represents a first predetermined natural number which is not less than two, a main storage which is divided into a common memory area accessed by said first through said N-th instruction processing units in common and first through N-th exclusive memory areas exclusively accessed by said first through said N-th instruction processing units, respectively, and first through N-th cache units connected in common to said main storage and connected to said first through said N-th instruction processing units, respectively, an n-th cache unit including an n-th cache memory, where n is variable between 1 and N, both inclusive, said n-th cache memory being divided into first through M-th block areas for memorizing memory blocks fetched from said main storage as first through M-th memorized blocks, respectively, where M represents a second predetermined natural number which is not less than two, the improvement wherein said n-th cache unit comprises common-block flag means divided into first through M-th flag bit areas corresponding to said first through said M-th block areas, respectively, an m-th flag bit area memorizing an m-th flag bit corresponding to an m-th memorized block to indicate presence or absence of one of said memory blocks in said common memory area in correspondence to said m-th memorized block, where m is variable between 1 and M, both inclusive.
Claim 2
Dependent Claim
231 words
In a multiprocessor system comprising first through N-th instruction processing units where N represents a first predetermined natural number which is not less than two, a main storage which is divided into a common memory area accessed by said first through said N-th instruction processing units in common and first through N-th exclusive memory areas exclusively accessed by said first through said N-th instruction processing units, respectively, and first through N-th cache units connected in common to said main storage and connected to said first through said N-th instruction processing units, respectively, an n-th cache unit including an n-th cache memory, where n is variable between 1 and N, both inclusive, said n-th cache memory being divided into first through M-th block areas for memorizing memory blocks fetched from said main storage as first through M-th memorized blocks, respectively, where M represents a second predetermined natural number which is not less than two, the improvement wherein said n-th cache unit comprises common-block flag means divided into first through M-th flag bit areas corresponding to said first through said M-th block areas, respectively, an m-th flag bit area memorizing an m-th flag bit corresponding to an m-th memorized block to indicate presence or absence of one of said memory blocks in said common memory area in correspondence to said m-th memorized block, where m is variable between 1 and M, both inclusive.
Claim 3
Dependent Claim
94 words
A multiprocessor system as claimed in Claim 1, an n-th instruction processing unit supplying said n-th cache unit with an n-th cache clear request indicative of clear of said n-th cache memory, wherein said n-th cache unit comprises cache clear means connected to said common-block flag means and to said n-th cache memory and responsive to said n-th cache clear request for clearing said n-th cache memory so as to erase said m-th memorized block when said m-th flag bit indicates presence of said one of the memory blocks in said common memory area.
Claim 4
Dependent Claim
224 words
A multiprocessor system as claimed in Claim 1 or 2, an n-th instruction processing unit supplying said n-th cache unit with an n-th fetch request indicative of fetch of a particular one of the memory blocks, said n-th cache unit comprising a block fetching circuit connected to said main storage and to said n-th cache memory for fetching, as a fetched block, said particular one of the memory blocks from said main storage in response to said n-th fetch request when said particular one of the memory blocks is absent in said n-th cache memory for said n-th fetch request, said block fetching circuit storing said fetched block into an m-th block area as said m-th memorized block, wherein said n-th cache unit comprises: common-block fetch detecting means connected to said block fetching circuit for detecting whether said particular one of the memory blocks is present or absent in said common memory area, said common-block fetch detecting means producing a detection signal when said particular one of the memory blocks is present in said common memory area; and common-block flag setting means connected to said common-block fetch detecting means and to said common-block flag means for setting said m-th flag bit indicative of presence of said particular one of the memory blocks in said m-th flag bit area in response to said detection signal.