EP0362425A1
Expired / Lapsed
EP
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Input/output controller incorporating address mapped input/output windows and read ahead/write behind capabilities
Assignee: Advanced Micro Devices Inc
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Filing: 1988-10-05
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Granted: —
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Expires: 2008-10-05
Abstract
Abstract Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. The aforesaid transfer function is accomplished in a manner that facilitates communication between the first and second set of devices from the comparatively lower performance of the second set of devices. According to the preferred embodiment, an input/output controller i.e., ("IOC") is disclosed that includes a set of address mapped I/O ports. The I/O ports may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting IOC interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance. Additionally, the IOC may be used as part of a data transfer controller ("DTC") having other components, such as direct memory access means, or may be used independently for transferring data between unmatched buses in, for example, RISC and non-RISC systems and data transmission systems generally.
Inventors
- 👤 William Michael Johnson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 17:09
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/4009; G06F13/4013
Claims Analysis
Total Claims: 66
Claim 1
Independent Claim
153 words
An input/output controller for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of relatively lower performance devices is attached, wherein the transferring of data to and from said first and second buses facilitates communication between said first and second set of devices while insulating the performance of said first set of devices from the comparatively lower performance of said second set of devices comprising: (a) input/output controller means, coupled to said first bus and to said second bus, including at least one address mapped input/output port means, for providing direct access to said second set of devices by said CPU; (b) means for interconnecting said first bus to said input/output controller means; and (c) means for interconnecting said second bus to said input/output controller means.
Claim 2
Dependent Claim
153 words
An input/output controller for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of relatively lower performance devices is attached, wherein the transferring of data to and from said first and second buses facilitates communication between said first and second set of devices while insulating the performance of said first set of devices from the comparatively lower performance of said second set of devices comprising: (a) input/output controller means, coupled to said first bus and to said second bus, including at least one address mapped input/output port means, for providing direct access to said second set of devices by said CPU; (b) means for interconnecting said first bus to said input/output controller means; and (c) means for interconnecting said second bus to said input/output controller means.
Claim 3
Dependent Claim
47 words
An input/output controller as set forth in claim 1 wherein said means for interconnecting said second bus to said controller means further comprises packing and funneling network means, coupled to said controller means, for accommodating variable width data transfers between said first bus and said second bus.
Claim 4
Dependent Claim
26 words
An input/output controller as set forth in claim 2 further comprising means for prioritizing access to said port means whenever a plurality of port means exist.
Claim 5
Dependent Claim
21 words
An input/output controller as set forth in claim 3 further comprising means for checking parity for both data and address transfers.
Claim 6
Dependent Claim
25 words
An input/output controller as set forth in claim 1 including a set of internal registers for controlling and maintaining the status of said port means.
Claim 7
Dependent Claim
30 words
An input/output controller as set forth in claim 5 wherein said means for interconnecting said first bus to said controller means further comprises means for initializing said set of registers.
Claim 8
Dependent Claim
30 words
An input/output controller as set forth in claim 1 further comprising means for overlapping port means operation with the operation of said set of devices attached to said first bus.
Claim 9
Dependent Claim
18 words
An input/output controller as set forth in claim 1 further comprising means for performing data packing and unpacking.
Claim 10
Dependent Claim
24 words
An input/output controller as set forth in claim 1 further comprising means for swapping data packet location in words being transferred via the controller.
Claim 11
Dependent Claim
41 words
An input/output controller as set forth in claim 6 further comprising a plurality of signal paths used for carrying CPU and device generated signals to and from said set of internal registers, which serve to initialize and control data transfer operations.
Claim 12
Dependent Claim
23 words
An input/output controller as set forth in claim 10 wherein said plurality of signal paths comprise the pins of an integrated circuit package.
Claim 13
Dependent Claim
29 words
An input/output controller as set froth in claim 1 further comprising means for decoupling the operation of port means within said contoller means from program execution by said CPU.
Claim 14
Dependent Claim
29 words
An input/output controller as set forth in claim 12 wherein said decoupling is accomplished via means for performing overlapped input/output via the implementation of a read ahead/write behind operation.
Claim 15
Dependent Claim
32 words
An input/output controller as set forth in claim 2 further comprising means for determining if a first bus address input to said port means is within a preselected port means address space.
Claim 16
Dependent Claim
53 words
An input/output controller as set forth in claim 14 wherein each of said input/output port means further comprises means for performing address translation between a first bus address input to the port and a second bus address to be output from the port, whenever the port is being addressed by said first bus.
Claim 17
Dependent Claim
37 words
An input/output controller as set forth in claim 15 wherein said address translation is performed over a power of two range of addresses of said first bus to an independent range of addresses of said second bus.
Claim 18
Dependent Claim
52 words
An input/output controller as set forth in claim 16 wherein said means for performing said address translation further comprises means for masking out a preselected number of high order bits from the first bus address and replacing said bits with the same number of high order bits of a second bus address.
Claim 19
Dependent Claim
30 words
An input/output controller as set forth in claim 17 wherein each of said port means further comprises means for multiplexing data to and from said packing and funneling network means.
Claim 20
Dependent Claim
38 words
An input/output controller as set forth in claim 13 wherein each of said port means further comprises a pack/funnel register for buffering data being transferred to and from said packing and funneling network means by said port means.
Claim 21
Dependent Claim
74 words
An input/output controller as set forth in claim 19 wherein said means for performing overlapped input/output further comprises: (a) means for determining if a given port means is enabled to perform a read ahead/write behind operation instead of direct read/write operation; and (b) means for immediately responding to an access by said first bus whenever a read ahead/write behind operation is enabled even though an access by said second bus may be in progress.
Claim 22
Dependent Claim
62 words
An input/output controller as set forth in claim 20 wherein said means for responding further comprises: (a) means for latching the address of said first bus access; (b) means for determining if said access is a read; and (c) means for performing said read, independent of any access on said second bus, whenever it is determined that said access is a read.
Claim 23
Dependent Claim
35 words
An input/output controller as set forth in claim 21 further comprising means for performing a write, independent of any access on said second bus, whenever it is determined that said access is not a read.
Claim 24
Dependent Claim
115 words
An input/output controller as set forth in claim 22 wherein said means for performing said read further comprises: (a) means, coupled to said first bus, for immediately transferring the contents of said pack/funnel register to said first bus whenever a given port means is accessed by a first bus read; (b) means, coupled to said first bus, for buffering the untranslated input address of the first bus access; (c) means, coupled to said means for buffering untranslated addresses, for translating said input address; and (d) means, coupled to said second bus, for performing a second bus read using said translated address and for storing the data read off said second bus in said pack/funnel register.
Claim 25
Dependent Claim
34 words
An input/output controller as set forth in claim 23 further comprising means, coupled to said pack/funnel register, for obtaining packed data from said packing and funneling network means for storage in said pack/funnel register.
Claim 26
Dependent Claim
34 words
An input/output controller as set forth in claim 24 further comprising means for inhibiting a subsequent access to a given port via said first bus while said port performs a read ahead/write behind operation.
Claim 27
Dependent Claim
116 words
An input/output controller as set forth in claim 25 wherein said means for performing said write further comprises: (a) means, coupled to said first bus, for storing data being transferred from said first bus to said second bus, via said port means, in said pack/funnel register whenever said port means is accessed by a first bus write; (b) means, coupled to said first bus, for buffering the untranslated input address of the first bus access; (c) means, coupled to said means for buffering untranslated addresses, for translating said input address; and (d) means, coupled to said second bus, for performing a second bus write using said translated address and the data stored in said pack/funnel register.
Claim 28
Dependent Claim
37 words
An input/output controller as set forth in claim 26 further comprising means, coupled to said pack/funnel register, enabling data to be funneled from said pack/funnel register to said second bus via said packing and funneling network means.
Claim 29
Dependent Claim
34 words
An input/output controller as set forth in claim 27 further comprising means for inhibiting a subsequent access to a given port via said first bus while said port performs a read ahead/write behind operation.
Claim 30
Dependent Claim
57 words
An input/output controller as set forth in claim 13 further comprising means for performing said read ahead and write behind operations in parallel wherein a first one of said port means is utilized to perform said read ahead function while a second one of said port means is used to perform the write behind function in parallel.
Claim 31
Dependent Claim
91 words
An input/output controller as set forth in claim 2 wherein said packing and funneling network means further comprises: (a) means for packing data on a transfer from said second bus to said first bus, including means for converting a number of byte and half work transfers on said second bus to a smaller number of half words and word transfers on said first bus; and (b) means for buffering data being packed, by said means for packing, in order to facilitate full word transfers of packed data to said first bus.
Claim 32
Dependent Claim
104 words
An input/output controller as set forth in claim 2 wherein said packing and funneling network means further comprises: (a) means for funneling data on a transfer from said first bus to said second bus, including means for converting a number of word and half word transfers on said first bus to a larger number of half word and byte transfers on said second bus; and (b) means for buffering data being funneled, by said means for funneling, in order to enable said means for funneling to extract half words and bytes of buffered data one at a time for transfer to said second bus.
Claim 33
Dependent Claim
26 words
An input/output controller as set forth in claim 1 further comprising: (a) means for supporting internal programmed input/output; and (b) means for supporting remotely programmed input/output.
Claim 34
Dependent Claim
42 words
An input/output controller as set forth in claim 1 further comprising means for decoupling the latency and bandwidth of accesses on said first bus from the latency and bandwidth of accesses on said second bus, with concurrency between accesses on both buses.
Claim 35
Dependent Claim
17 words
An input/output controller as set forth in claim 1 suitable for transferring data between two synchronous buses.
Claim 36
Dependent Claim
17 words
An input/output controller as set forth in claim 1 suitable for transferring data between two asynchronous buses.
Claim 37
Dependent Claim
26 words
An input/output controller as set forth in claim 1 having a test mode of operation which allows the controller outputs to be driven for diagnositc purposes.
Claim 38
Dependent Claim
27 words
An input/output controller as set forth in claim 1 operable in parallel with at least one input/output controller, to which it is connected, in a master/slave relationship.
Claim 39
Independent Claim
117 words
A method for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of relatively lower performance devices is attached, comprising the steps of: (a) transferring data between said first bus and said second bus utilizing input/output controller means, including at least one address mapped input/output port means, coupled to said buses; and (b) insulating, via said port means, the performance of said first set of devices from the comparatively lower performance of said second set of devices when transferring data between said first and second bus via said controller means.
Claim 40
Independent Claim
117 words
A method for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of relatively lower performance devices is attached, comprising the steps of: (a) transferring data between said first bus and said second bus utilizing input/output controller means, including at least one address mapped input/output port means, coupled to said buses; and (b) insulating, via said port means, the performance of said first set of devices from the comparatively lower performance of said second set of devices when transferring data between said first and second bus via said controller means.
Claim 41
Dependent Claim
31 words
A method as set forth in claim 38 further comprising the step of packing data being transferred from said second bus to said first bus to accommodate variable width data transfers.
Claim 42
Dependent Claim
31 words
A method as set forth in claim 39 further comprising the step of funneling data being transferred from said first bus to said second bus to accommodate variable width data transfers.
Claim 43
Dependent Claim
29 words
A method as set forth in claim 38 further comprising the step of multiplexing address signals and data signals being transferred to said second bus by said controller means.
Claim 44
Dependent Claim
26 words
A method as set forth in claim 41 further comprising the step of prioritizing access to said port means whenever a plurality of port means exists.
Claim 45
Dependent Claim
21 words
A method as set forth in claim 38 further comprising the step of checking parity for both data and address transfers.
Claim 46
Dependent Claim
24 words
A method as set forth in claim 38 further comprising the step of initializing a set of registers used for controlling said channel means.
Claim 47
Dependent Claim
39 words
A method as set forth in claim 38 wherein said step of insulating via said port means further comprises the step of overlapping port means operation with the operation of said set of devices attached to said first bus.
Claim 48
Dependent Claim
39 words
A method as set forth in claim 38 wherein the step of insulating via said port means further comprises the step of decoupling the operation of said port means within said controller means from program execution by said CPU.
Claim 49
Dependent Claim
27 words
A method as set forth in claim 46 wherein said decoupling is accomplished via performing overlapped input/output through the implementation of read ahead and write behind operations.
Claim 50
Dependent Claim
32 words
A method as set forth in claim 38 further comprising the step of determining if a first bus address input to said port means is within a preselected port means address space.
Claim 51
Dependent Claim
43 words
A method as set forth in claim 48 further comprising the step of translating a first bus address input to a port to a second bus address to be output from the port, whenever the port is being addressed by said first bus.
Claim 52
Dependent Claim
49 words
A data transfer controller as set forth in claim 49 wherein said step of translating is performed by masking out a preselected number of high order bits from the first bus address and replacing said bits with the same number of high order bits of a second bus address.
Claim 53
Dependent Claim
32 words
A method as set forth in claim 47 wherein said step of decoupling further comprises the step of buffering data being transferred by said port means to and from said second bus.
Claim 54
Dependent Claim
72 words
A method as set forth in claim 51 wherein said step of performing overlapped input/output further comprises the steps of: (a) determining if a given port means is enabled to perform a read ahead/write behind operation instead of direct read/write operation; and (b) responding immediately to an access by said first bus whenever a read ahead/write behind operation is enabled even though an access by said second bus may be in progress.
Claim 55
Dependent Claim
60 words
A data transfer controller as set forth in claim 52 wherein said step of responding further comprises the steps of: (a) latching the address of said first bus access; (b) determining if said access is a read; and (c) performing said read, independent of any access on said second bus, whenever it is determined that said access is a read.
Claim 56
Dependent Claim
35 words
A method as set forth in claim 53 further comprising the step of performing a write, independent of any access on said second bus, whenever it is determined that said access is not a read.
Claim 57
Dependent Claim
91 words
A method as set forth in claim 54 wherein said step of performing said read further comprises the steps of: (a) transferring packed data, stored in said port means, to said first bus whenever a given port means is accessed by a first bus read; (b) buffering the untranslated input address of the first bus access; (c) translating said input address to a corresponding second bus address; (d) reading data off said second bus using said translated address; and (e) storing data read off said second bus in said port means.
Claim 58
Dependent Claim
34 words
A method as set forth in claim 55 further comprising the step of inhibiting a subsequent access to a given port via said first bus while said port performs a read ahead/write behind operation.
Claim 59
Dependent Claim
95 words
A data transfer controller as set forth in claim 56 wherein said step of performing said write further comprises the steps of: (a) storing data being transferred from said first bus to said second bus, via said port means, in said port means whenever said port means is accessed by a first bus write; (b) buffering the untranslated input address of the first bus access; (c) translating said input address to a corresponding second bus address; and (d) performing a second bus write using said translated address and the data stored in said port means.
Claim 60
Dependent Claim
30 words
A method as set forth in claim 57 further comprising the step of funneling data from said port means to said second bus via a packing and funneling network means.
Claim 61
Dependent Claim
34 words
A method as set forth in claim 58 further comprising the step of inhibiting a subsequent access to a given port via said first bus while said port performs a read ahead/write behind operation.
Claim 62
Dependent Claim
57 words
A method as set forth in claim 47 further comprising the step of performing said read ahead and write behind operations in parallel wherein a first one of said port means is utilized to perform said read ahead function while a second one of said port means is used to perform the write behind function in parallel.
Claim 63
Dependent Claim
80 words
A method as set forth in claim 38 further comprising the steps of: (a) packing data on a transfer from said second bus wherein said step of packing further includes the step of converting a number of byte and half word transfers on said second bus to a smaller number of half words and word transfers on said first bus; and (b) buffering data being packed in order to facilitate full word transfers of packed data to said first bus.
Claim 64
Dependent Claim
63 words
A method as set forth in claim 38 further comprising the step of funneling data on a transfer from said first bus to said second bus wherein said step of funneling further includes the step of converting a number of word and half word transfers on said first bus to a larger number of half word and byte transfers on said second bus.
Claim 65
Dependent Claim
43 words
A method as set forth in claim 62 wherein said step of converting further comprises the steps of: (a) buffering data being funneled; and (b) extracting half words and bytes of buffered data, one at a time, for transfer to said second bus.
Claim 66
Dependent Claim
42 words
A method as set forth in claim 63 further comprising the step of decoupling the latency and bandwidth of accesses on said first bus from the latency and bandwidth of accesses on said second bus, with concurrency between accesses on both buses.
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