Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
164 words
sinqle chip microprocessor with a microprocessing unit and external signal pine to which off-chip devices arc connectable, characterized by ar interface control unit, said interface control unit being connected to said microprocessing unit and to said external signal pins of said single-chip microprocessor, said microprocessing unit and said interface control unit being logically distinct elements, surh that said interface control unit is logically transportable for use with other and different microprocessing units; said interface control unit providing means for said microprocessing unit and said off-chip devices connected to said pins to communicate with one another, said means being responsive to commands from said microprocessing unit and to control signals from said off-chip devices, wherein when said microprocessing unit transmits a command to said interface control unit requesting a particular data transfer, said means performs said data transfer and, upon logical completion of said data transfer, presents a status output to said microprocessing unit, said status output describing the outcome of said command. (Fig 1)
Claim 2
Dependent Claim
164 words
sinqle chip microprocessor with a microprocessing unit and external signal pine to which off-chip devices arc connectable, characterized by ar interface control unit, said interface control unit being connected to said microprocessing unit and to said external signal pins of said single-chip microprocessor, said microprocessing unit and said interface control unit being logically distinct elements, surh that said interface control unit is logically transportable for use with other and different microprocessing units; said interface control unit providing means for said microprocessing unit and said off-chip devices connected to said pins to communicate with one another, said means being responsive to commands from said microprocessing unit and to control signals from said off-chip devices, wherein when said microprocessing unit transmits a command to said interface control unit requesting a particular data transfer, said means performs said data transfer and, upon logical completion of said data transfer, presents a status output to said microprocessing unit, said status output describing the outcome of said command. (Fig 1)
Claim 3
Dependent Claim
157 words
Microprocessor according to claim 1, characterized by said interface control unit comprising: execution means (Figs 21, 23, 26) connected to said microprocessing unit and to said external signal pins of said single-chip microprocessor; and contiol means (Fig 28) for cantrolling said execution means and for performing signal sequencing at said external signal pins, said signal sequencing beinq called a bus cycle, said control means being responsive to commands from said co-resident microprocessing unit and to control signals from said off-chip devices; said control means including command means responsive to said commands from said co-resident microprocessing unit and status means for presenting status to said co--resident microprocessing unit describing the outcome of each command, wherein said command means causes said execution means to perform a particular data transfer in response to a particular command from said co-resident microprocessing unit, and said status means presents the outcome status of said particular command upon logical completion of said data transfer.
Claim 4
Dependent Claim
69 words
Microprocessor according to claims 1 and 2 wherein said execution means and said control means are designed to provide an external appearance at said external signal pins that is compatible with the peripheral devices of a specific micro- processor called the compatible microprocessor, thereby enabling at least one peripheral device of said compatible microprocessor to be attached to said single-chip microprocessor and to communicate with said co-resident microprocessing unit.
Claim 5
Dependent Claim
45 words
Microprocessor according to claim 3 wherein said execution means and control means further include extended means for attaching and operating other peripheral devices not associated with said compatible microprocessor, said extended means and its operation being transparent to any co-attached device of said compatible microprocessor.
Claim 6
Dependent Claim
89 words
Microprocessor according to claim 4 wherein said extended means comprises: means for generating non-compatible signals not physically detectable by any attached device of said compatible microprocessor; and means for generating compatible rianals physically detectable by, but log:cally transparent to, all attached devices of said compatable microprocessor, said compatible signals conforming to the natural communicationprotocol of the devices of said compatible microprocessor, said other peripheral devices not associated with said compatible microprocessor using said non-compatible signals and said compatible signals in the process of communicating with said interface control unit.
Claim 7
Dependent Claim
32 words
Microprocessor according to claim 4 wherein said control means includes mixed-width device handling means for dynamically controlling said execution means in response to an addressed cevice's width-identifying response to a bus cycle.
Claim 8
Dependent Claim
38 words
Microprocessor accordinq to claim 4 wherein said control means includes accessing means for accessing operands from said off-chip devices at any byte location including those locations which do not correspond to an integral boundary of the accessed operand.
Claim 9
Dependent Claim
25 words
Microprocessor according to claim 4 wherein said control means is responsive to an external control signal for varying the minimum duration of a bus cycle.
Claim 10
Dependent Claim
59 words
Microprocessor according to claim 2 wherein said control means further comprises: initiation sequence means for generating initiation signals identifying said bus cycle to at least one off-chip device; detection sequence means for seeking and responding to the oxternal signals produced by said off-chip device in response to said initiation signals; and termination sequence means for concluding said bus cycle.
Claim 11
Dependent Claim
93 words
Microprocessor according to claim 2 wherein said control means further comprises: bus arbitration means for granting temporary and exclusive use to an off-chip master device of any bus derived from said external pins of said single-chip microprocessor, said arbitration moans being logically independent of said control means responsive to said commands from said co-resident microprocessing unit, and said qran- ting being subject to enablement by said control means as a condition for being exhibited to said off-chip master device; and bus grant enable means for enabling and disabling said granting of said bus.