Memory circuit provided with improved redundant structure

Claim 2

A memory circuit comprising a first number of memory blocks, each of said memory blocks having a plurality of memory cells, a plurality of peripheral circuit blocks of said first number provided for said memory blocks, respectively, each of said peripheral circuits operatively deriving a read signal at its output end from the associated memory blocks, a second number of output terminals, said second number being smaller than said first number, and a programmable switch circuit for selectively causing signal paths between said second number of output terminals and the output ends of said second number of peripheral circuit blocks, whereby the remaing peripheral circuit block or blocks other than said second number of peripheral circuit blocks are fixedly isolated from any of said output terminals.

Claim 3

The memory circuit according to claim 1, in which said memory blocks have a plurality of word lines in common.

Claim 4

The memory circuit according to claim 1, in which each of said peripheral circuit blocks includes a column selection circuit for selecting one of columns of the associated memory block and a buffer circuit for amplifying a signal from the selected column

Claim 5

The memory circuit according to claim 1, in which said programmable switch circuit includes a plurality of switch units of said first number, each of said switch units having a common node and a plurality of switch nodes to be selectively connected to the common node, the common node of each of said switch units being connected to the output end of the associated peripheral circuit block, each of said output terminals being electrically coupled to the switch nodes of the different two or more switch units, and a plurality of programmable control means for controlling conductive states of said switch units.

Claim 6

A memory circuit comprising a memory cell array having a plurality of word lines arranged in rows, a plurality of bit lines arranged in columns perpendicular to said rows, and a plurality of memory cells coupled to said word lines and bit lines, said plurality of bit lines being divided into a plurality of bit line groups, means for selecting one of said word lines, a plurality of bit line selection circuits provided for said bit line groups, each of said bit line selection circuits having an output end and selectively establishing a signal path between the output end and one of the bit lines of the associated bit line group, a plurality of input/output buffers, each of said input/output buffers being coupled to the output end of the associated bit line selection circuit, a plurality of switch circuits provided for said plurality of input/output buffers, each of said switch circuits having a common node coupled to the associated input/output buffer and first and second switch nodes to be selectively coupled to the common node, a plurality of program circuits provided for said switch circuits, each of said program circuits setting conductive state of the associated switch circuit according to program state thereof, and a plurality of input/output terminals, the number of said input/output terminals being less than the number of said switch circuits, each of said input output terminals being connected two or more of said switch circuits, whereby good input/output buffers associated with good bit line groups are coupled to said input/output terminals through the switch circuits while defective input/output buffer or buffers or the input/output buffer or buffers associated with defective bit line groups are fixedly isolated from said input/output terminals.

Claim 7

A memory circuit comprising a memory cell array having a plurality of word lines arranged in rows, a plurality of bit lines arranged in columns perpendicular to said rows, and a plurality of memory cells coupled to said word lines and bit lines, said plurality of bit lines being divided into a plurality of bit line groups, means for selecting one of said word lines, a plurality of bit line selection circuits provided for said bit line groups, each of said bit line selection circuits having an output end and selectively establishing a signal path between the output end and one of the bit lines of the associated bit line group, a plurality of input/output buffers, each of said input/output buffers being coupled to the output end of the associated bit line selection circuit, a plurality of switch circuits provided for said plurality of input/output buffers, each of said switch circuits having a common node coupled to the associated input/output buffer and first and second switch nodes to be selectively coupled to the common node, a plurality of program circuits provided for said switch circuits, each of said program circuits setting conductive state of the associated switch circuit according to program state thereof, and a plurality of input/output terminals, the number of said input/output terminals being less than the number of said switch circuits, each of said input output terminals being connected two or more of said switch circuits, whereby good input/output buffers associated with good bit line groups are coupled to said input/output terminals through the switch circuits while defective input/output buffer or buffers or the input/output buffer or buffers associated with defective bit line groups are fixedly isolated from said input/output terminals.