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EP0359551B1
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EP
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Semicoductor memory circuit
Assignee: JFE Steel Corp
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Filing: 1989-09-13
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Granted: 1994-12-28
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Expires: 2009-09-13
Abstract
No abstract record available.
Inventors
- 👤 Toshikazu Ishii
- 👤 Norimitsu Sako
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:45
CPC Classifications
G; G11; G11C; G11C7/00; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G11C7/10; G11C7/1006
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
216 words
A semiconductor memory circuit capable of changing the numbers of bits and words associated therewith, the circuit comprising:- chip control means (10, 30) for at least selecting the number of bits of one word and for switching between a random access memory mode and a first-in first-out memory mode; an address buffer (12) having a function to alter an effective address length on the basis of a selected bit construction; address counter means (14; 14A, 14B) connected to an output of said address buffer (12), for counting up a write address or a read address in each write or read operation when the first-in first-out memory function has been selected; a memory cell array (16A, 16B) including memory cells selectively operable in either of said random access memory mode and said first-in first-out memory mode; column and line decoder means (18A, 18B, 20; 34A, 34B, 36A, 36B, 20A, 20B) interposed between said address counter means and said memory cell array, for controlling said memory cell array on the basis of the selected bit construction; and input/output buffer means (22; 22A, 22B) connected to column decoder means (18A, 18B; 34A, 34B, 36A, 36B) of said column and line decoder means, having a function to change an effective data length on the basis of the selected bit construction.
Claim 2
Dependent Claim
24 words
A circuit according to claim 1, wherein the write and read operations are independently executable when the first-in first-out memory mode has been selected.
Claim 3
Dependent Claim
29 words
A circuit according to claim 1 or 2, further comprising programming means (30A) which are programmable to determine whether the memory circuit itself is to be used or not.
Claim 4
Dependent Claim
43 words
A circuit according to claim 1, 2, or 3 which further comprises an input/output selection switch (50) for enabling at least part of an input of said address buffer (12), and inputs and outputs of said input/output buffer means (22) to be selected.
Claim 5
Dependent Claim
42 words
A circuit according to any preceding claim, wherein said chip control means (10) monitors counted values by said address counter means (14), and issues an alarm signal (AWNG) when an address, where no information has been written, is assigned for read out.
Claim 6
Dependent Claim
189 words
A circuit according to claim 1, further comprising:- write and read address counters (14A, 14B), constituting said address counter means and provided separately for counting up write and read addresses independently at each write and read operation when the first-in first-out memory mode has been selected; write address switching means (32A) for making valid an address input from said address buffer (12) when the random access memory mode has been selected, while making valid an address input from said write address counter when the first-in first-out memory mode has been selected; and read address switching means (32B) for making valid an address input from said address buffer when the random access memory mode has been selected, while making valid an address input from said read address counter when the first-in first-out memory mode has been selected; input and output buffers (22A, 22B) constituting said input/output buffer means and provided separately, having a function to change an effective data length based upon the selected bit construction; and wherein said input/output buffer means comprises write column and line decoders (34A, 36A, 20A) and read column and line decoders (36>B, 34B, 20B).
Claim 7
Dependent Claim
86 words
A circuit according to claim 6, wherein each memory cell of said memory cell array is astatic random access memory composed of inverters (40, 42) for holding information, and selection transistors (44, 46, 48) for connecting and separating each memory cell to and from bit lines (bit - w, bit - r, bit - w ) in conformity with a level of word lines (word - w, word - r), and the word lines and the bit lines are independently provided for write and read operations.
Claim 8
Dependent Claim
30 words
A circuit according to claim 6 or 7, wherein when the write address and the read address are coincident with each other, a write operation has priority to be executed.
Claim 9
Dependent Claim
43 words
A circuit according to claim 6, 7 or 8, wherein the write operation is interrupted when the write address is filled up upon the write operation, and the write operation is restarted from the oldest address when a write reset signal is entered.
References Cited (Backward Citations)
No citation records indexed.
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