Patent EP0359525B1 successfully refreshed from Google Patents.
EP0359525B1
Expired / Lapsed
EP
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Continuous semiconductor substrate processing system
Assignee: Fujitsu Ltd
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Filing: 1989-09-12
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Granted: 1995-02-22
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Expires: 2009-09-12
Abstract
No abstract record available.
Inventors
- 👤 Tadashi Kiriseko
- 👤 Hiromichi Tani
- 👤 Noriko Soma
- 👤 Nobuhisa Shigemi
- 👤 Takayuki Toyoda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 02:50
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/04; H10P72/0451; H10P72/0452; H10P72/0456; H10P72/06; H10P72/0612; H10P72/0618; H10P72/30; H10P72/32; H10P72/3216; Y; Y10; Y10S; Y10S414/00; Y10S414/135; Y10S414/137; Y10S414/14
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
339 words
A continuous semiconductor substrate processing system including a plurality of different process stations (5) for performing respective predetermined processes on semiconductor wafers, and a conveying mechanism (4) conveying semiconductor wafers between said individual semiconductor wafer process stations (5) and provided with a control section (9), said system comprising:- interface sections (6) provided between said conveying mechanism (4) and each of said process stations (5), respectively, each of the interface sections (6) including a first transfer mechanism (11) for transferring the semiconductor wafers between said conveying mechanism (4) and the respective process station (5); a stocker (7) coupled to said conveying mechanism (4) for temporarily accommodating the semiconductor wafers during the processing and including a storage section (15) for storing said semiconductor wafers and a second transfer mechanism (14) for transferring semiconductor wafers between said storage section (15) and said conveying mechanism (4), said stocker further comprising a discrimination section (16); and a system control section (10) communicating with and controlling said process stations (5), interface sections (6), stocker (7) and conveying mechanism control section (9); characterised in that:- said system manages wafers on a one-by-one basis, said conveying mechanism (4) and said first transfer mechanism (11) handling individual said wafers; each of said interface sections (6) further includes a discrimination section (13) for discriminating individual said semiconductor wafers, and a buffer section (12) temporarily storing said semiconductor wafers and comprising a carrier which can carry semiconductor wafers and which can be mounted in and dismounted from said interface section (6); the discrimination section (16) of the stocker (7) discriminates individual semiconductor wafers; the stocker (7) further comprises a carrier feed-in/feed-out section (17) capable of mounting and dismounting of said carrier for feeding in and feeding out said semiconductor wafers; and in that:- said system control section (10) is operable to determine the priority order of processing of said individual semiconductor wafers stored in said buffer section (12) and to order said transfer mechanism (11) to transfer said individual semiconductor wafers in the decided order to the process stations (5).
Claim 2
Dependent Claim
35 words
A continuous semiconductor wafer processing system according to claim 1, which further comprises an inspection station (8) coupled to said conveying mechanism (4) for inspecting semiconductor wafers processed in each of said process stations (5).
Claim 3
Dependent Claim
30 words
A continuous semiconductor wafer processing system according to claim 1 or 2, wherein said carrier is adapted to be mounted in said carrier feed-in/feed-out section (17) of said stocker (7).
Claim 4
Dependent Claim
261 words
A continuous semiconductor wafer processing system according to claim 1, 2 or 3, wherein:- said conveying mechanism (4) conveys semiconductor wafers; said system control section (10) communicates with and thereby controls said process stations (5), interface sections (6), stocker (7) and conveying mechanism control section (9) for conveying semiconductor wafers to each of said process stations (5) according to a procedure preliminarily programmed therein so that said wafers may be continuously processed; said individual semiconductor wafers are conveyed to said stocker (7) if a next process station (5), to which said semiconductor wafers are to be conveyed, is holding work in excess of a permissible amount of semiconductor wafers, said semiconductor wafers conveyed to said stocker (7) being discriminated in a discrimination section (16) and then stored in a storage section (15); when said next process station becomes ready to receive semiconductor wafers, said semiconductor wafers in said storage section (16) of said stocker (7) being taken out sequentially according to a program of said system control section (10), to be discriminated in said discrimination section (16) and then conveyed to said next process station; and the priority order of processing individual semiconductor wafers in each said process station (5) is determined by said system control section (10) through communication thereof with the associated interface section (6), said determination being carried out sequentially with respect to semiconductor wafers which have been discriminated in said discrimination section (13) of said interface section (6) and then stored in said buffer section (12) thereof according to a program of said system control section (10).
Claim 5
Dependent Claim
79 words
The continuous semiconductor wafer processing system according to claim 1, 2, 3 or 4, wherein a plurality of identical process stations (5-11, 5-12, ...) for performing the same process are provided as each of said process stations (5), and semiconductor wafers are conveyed to the next process station (5) by selecting one of said plurality of identical process stations (5-11, 5-12, ...), the buffer section (12) of the associated interface section (6) of which has the greatest prevailing capacity.
Claim 6
Dependent Claim
293 words
The continuous semiconductor wafer processing system according to claim 4 as appended to claim 3, wherein, when a fault occurs in or during maintenance of said conveying mechanism (4), semiconductor wafers are conveyed without said conveying mechanism (4); said control section (10) communicating with and thereby controlling said process sections (5), interface sections (6) and stocker (7) to ensure that semiconductor wafers are conveyed on a carrier-by-carrier basis to said process stations (5) according to a predetermined program of said system control section (10) so that said semiconductor wafers are continuously processed, said carrier being mounted in said carrier feed-in/feed-out section (17) of said stocker (7) when conveying said carrier from a process station to a next station; said semiconductor wafers in said carrier being individually discriminated in said discrimination section (16) of said stocker (7) and then temporarily stored in said storage section (15) thereof, only semiconductor wafers to be conveyed to said next process station being taken out from said storage section (15) according to an instruction from said system control section (10), to be individually discriminated in said discrimination section (16) and then accommodated in a carrier mounted in said carrier feed-in/out section (17); the carrier after completion of accommodation not being conveyed by said conveying mechanism (4) to said next process station; the priority order of processing of individual semiconductor wafers in each of said process stations (5) being determined by said system control section (10) through communication thereof with the associated interface section (6), said determination being carried out sequentially with respect to semiconductor wafers, which have been determined in said discrimination section (13) of said interface section (6) and then stored in said buffer section (12) thereof, according to a program of said system control section (10).
References Cited (Backward Citations)
No citation records indexed.
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