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EP0358501A2
Expired / Lapsed
EP
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Programmable input/output circuit
Assignee: JFE Steel Corp
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Filing: 1989-09-07
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Granted: —
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Expires: 2009-09-07
Abstract
Abstract In a programmable input/output circuit which is used in a programmable integrated circuit, for interfacing between an external circuit and an internal logic circuit, both disposed exterioly and interiorly of said integrated circuit, an input/output terminal(40) connected to a bus of the internal logic circuitg and a tri-state input buffer (44, 48) are provided, and hereby assured that an external input signal is transmitted to either of the input/output terminal and an ordinary input terminal(42) by switching the status of the tri-state input buffer. In a programmable logic device, which incorporates said input/output circuit, a tri-state buffer(106) is provided between an input/output circuit block(80) and a wiring element(102), and hereby a driving capability of the wiring element used as a bus line is increased.
Inventors
- 👤 Keiichi Kawana
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 14:38
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17744; H03K19/0175; H03K19/01759; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1778; H03K19/17792
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
113 words
A programmable input/output circuit for use in a programmable integrated circuit, for interfacing between an external circuit of the integrated circuit and an internal logic circuit of the same, the programmable input/output circuit comprising: (a) an input/output terminal(40) connected to a bus of the internal logic circuit; (h) an input terminal(42) connected to a programmable wiring of the internal logic circuit; (c) a tri-state input buffer(44, 48) for transmitting an input signal fed externally of the circuit to any one of said input/output terminal and said input terminal, and (d) a tri-state output buffer(24) for transmitting externally of the circuit an output signal from the internal logic circuit fed to said input/output terminal.
Claim 2
Dependent Claim
113 words
A programmable input/output circuit for use in a programmable integrated circuit, for interfacing between an external circuit of the integrated circuit and an internal logic circuit of the same, the programmable input/output circuit comprising: (a) an input/output terminal(40) connected to a bus of the internal logic circuit; (h) an input terminal(42) connected to a programmable wiring of the internal logic circuit; (c) a tri-state input buffer(44, 48) for transmitting an input signal fed externally of the circuit to any one of said input/output terminal and said input terminal, and (d) a tri-state output buffer(24) for transmitting externally of the circuit an output signal from the internal logic circuit fed to said input/output terminal.
Claim 3
Dependent Claim
30 words
A programmable input/output circuit according to claim 1, further comprising an input buffer(18) for converting said input signal from a TTL or CMOS logical level to an internal logical level.
Claim 4
Dependent Claim
60 words
A programmable input/output circuit according to claim 1 or 2, wherein said tri-state input buffer includes a first tri-state input buffer(44) for transmitting said input signal to said input/output terminal and a second tri-state input buffer(48) which is switched on and off in conformity with contents stored in a memory cell(M) for transmitting said input signal to said input terminal.
Claim 5
Dependent Claim
47 words
A programmable input/output circuit according to claim 3,further comprising a two-input multiplexer(50) including therein a memory cell, the multiplexer selecting any one of a chip enable signal and an earth signal entered through said input terminal as a status control signal for said first tri-state input buffer(44).
Claim 6
Dependent Claim
37 words
A programmable input/ ouput circuit accordingly to claim 1,2,3 or 4, wherein an on/off status of said output buffer(24) is controlled by an output enable signal applied from the internal logical circuit to an output control terminal.
Claim 7
Dependent Claim
46 words
A programmable input/output circuit according to any preceding claim, further comprising a pull-up resistor(51) for pulling up the potential of a pad(16), to which said input signal is applied, and a pass transistor(52) including therein a memory cell(M) for switching said pull-up resistor on and off.
Claim 8
Dependent Claim
38 words
A programmable input/output circuit according to any preceding claim, further comprising a D flip-flop(20) for latching various signals and a two-input multiplexer(22) for selecting any one of an output signal from said D flip-flop and an original signal.
Claim 9
Dependent Claim
58 words
A programmable input/output circuit according to any preceding claim, further comprising a first reset terminal(70) for receiving a reset signal, a second reset terminal(72) for receiving a global reset signal , and a NOR gate(74) for outputting as the reset signal the negation of a logical sum of the signals applied to said first and second reset terminal.
Claim 10
Dependent Claim
62 words
A programmable logic device including a programmable input/output circuit block(80), comprising: (a) an input/output control terminal(108, 110) provided in said input/output circuit block; (b) wiring means(102) capable of programming electrical connection; (c) a tri-state buffer(106) including an enable control input terminal, and wherein the enable control of said tri-state buffer is performed by a control signal generated in said input/output circuit block.
Claim 11
Dependent Claim
62 words
A programmable logic device including a programmable input/output circuit block(80), comprising: (a) an input/output control terminal(108, 110) provided in said input/output circuit block; (b) wiring means(102) capable of programming electrical connection; (c) a tri-state buffer(106) including an enable control input terminal, and wherein the enable control of said tri-state buffer is performed by a control signal generated in said input/output circuit block.
References Cited (Backward Citations)
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