Patent EP0358376A2 successfully refreshed from Google Patents.
EP0358376A2
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EP
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Integrated test circuit
Assignee: Texas Instruments Inc
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Filing: 1989-08-23
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Granted: —
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Expires: 2009-08-23
Abstract
Abstract A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.
Inventors
- 👤 Lee D. Whetsel, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 19:49
CPC Classifications
G; G11; G11C; G11C29/00; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; G01R31/318555
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
47 words
A boundary scan test cell for use in conjunction with an integrated circuit containing application logic circuitry comprising: a first memory for storing serial data and transmitting said serial data to other test cells; and a second memory connected to said first memory for storing output data.
Claim 2
Dependent Claim
47 words
A boundary scan test cell for use in conjunction with an integrated circuit containing application logic circuitry comprising: a first memory for storing serial data and transmitting said serial data to other test cells; and a second memory connected to said first memory for storing output data.
Claim 3
Dependent Claim
18 words
The test cell of Claim 1 and further comprising circuitry connecting said second memory to the application logic
Claim 4
Dependent Claim
25 words
The test cell of Claim 1 and further comprising circuitry to construct the output of said second memory to the input of the first memory.
Claim 5
Dependent Claim
23 words
The test cell of Claim 1 and further comprising hold circuitry to maintain the output of said second memory at a given state.
Claim 6
Dependent Claim
25 words
The test cell of Claim 1 and further comprising toggle circuitry to alternate the output of said second memory between first and second logic levels.
Claim 7
Dependent Claim
35 words
The test cell of Claim 1 wherein the output of said first memory is connected to the input of said second memory such that said second memory can be loaded with a predetermined logic value.
Claim 8
Dependent Claim
22 words
The test cell of Claim 1 and further comprising circuitry to connect said first memory to an input of the integrated circuit.
Claim 9
Dependent Claim
22 words
The test cell of Claim 1 and further comprising circuitry to connect said second memory to an output of the integrated circuit.
Claim 10
Dependent Claim
73 words
A boundary scan test cell comprising: a first memory; a first multiplexer for connecting one of a plurality of inputs to said first memory responsive to a first control signal; a second memory connected to the output of said first memory; and a second multiplexer for selecting an output from one of a set of inputs to the second multiplexer including the output of said second memory responsive to a second control signal.
Claim 11
Dependent Claim
73 words
A boundary scan test cell comprising: a first memory; a first multiplexer for connecting one of a plurality of inputs to said first memory responsive to a first control signal; a second memory connected to the output of said first memory; and a second multiplexer for selecting an output from one of a set of inputs to the second multiplexer including the output of said second memory responsive to a second control signal.
Claim 12
Dependent Claim
14 words
The test cell of Claim 9 wherein said first memory comprises a D-type flip-flop.
Claim 13
Dependent Claim
39 words
The test cell of Claim 10 and further comprising clock circuitry for producing a clock signal connected to said D-type flip-flop, such that the output of said first multiplexer is stored in said first memory at each clock pulse.
Claim 14
Dependent Claim
14 words
The test cell of Claim 9 wherein said second memory comprises a D-type latch.
Claim 15
Dependent Claim
32 words
The test cell of Claim 12 and further comprising control circuitry connected to said latch for producing a hold signal responsive to which said latch stores data output from said first memory
Claim 16
Dependent Claim
40 words
The test cell of Claim 9 wherein said second memory includes inverted and non-inverted outputs, said inverted output connected as one of said inputs to said first multiplexer, such that a toggled output may be produced by the test cell.
Claim 17
Dependent Claim
23 words
The test cell of Claim 9 wherein the output of said first memory is connected as one of said inputs to first multiplexer.
Claim 18
Dependent Claim
98 words
An integrated circuit having boundary scan testing, comprising: application logic circuitry having one or more inputs and one or more outputs; one or more data inputs for receiving data into the integrated circuit; one or more data outputs for outputing data from the integrated circuit; a test data input for receiving test data into the integrated circuit; one or more input test cells connected between respective data inputs and said application logic circuitry, said input test cells comprising: a first memory for storing serial data; and a second memory connected to said first memory for storing output data;
Claim 19
Dependent Claim
98 words
An integrated circuit having boundary scan testing, comprising: application logic circuitry having one or more inputs and one or more outputs; one or more data inputs for receiving data into the integrated circuit; one or more data outputs for outputing data from the integrated circuit; a test data input for receiving test data into the integrated circuit; one or more input test cells connected between respective data inputs and said application logic circuitry, said input test cells comprising: a first memory for storing serial data; and a second memory connected to said first memory for storing output data;
Claim 20
Dependent Claim
113 words
The integrated circuit of Claim 16 and further comprising: one or more output test cells connected between said application logic and respective data outputs, said output test cells comprising: a third memory for storing information; a fourth memory for storing information output from said third memory; a third multiplexer selectively connecting one of a plurality of inputs thereto to said third memory, one of said plurality of inputs being connected to said test data input; and a fourth multiplexer for selectively connecting one of a plurality inputs thereto to said respective data output, the respective output from said application logic and the output of said fourth memory being input to said second multiplexer.
Claim 21
Dependent Claim
45 words
The integrated circuit of Claim 16 and further comprising one or more output test cells connected between respective data outputs and said application logic circuit, said output test cells comprising: a first memory for storing serial data; and a second memory for storing output data.
Claim 22
Dependent Claim
32 words
The integrated circuit of Claim 16 wherein said integrated circuit includes a plurality of input test cells and further comprising circuitry for serially connecting ones of said first memories of input cells.
Claim 23
Dependent Claim
34 words
The integrated circuit of Claim 17 wherein said integrated circuit includes a plurality of output test cells and further comprising circuitry for serially connecting ones of said first memories of said output test cells.
Claim 24
Dependent Claim
38 words
The integrated circuit of Claim 17 and further comprising circuitry for connecting the output of said first memory of one of said input test cells to the input of said first memory of one of said output cells.
Claim 25
Dependent Claim
30 words
The integrated circuit of Claim 16 and further comprising circuitry for producing a binary counting function at the output of said second memories of ones of said input test cells.
Claim 26
Dependent Claim
30 words
The integrated circuit of Claim 17 and further comprising circuitry for producing a binary counting function at the output of said second memories of ones of said output test cells.
Claim 27
Independent Claim
99 words
A method of observing and controlling information input to an output from an integrated circuit containing application logic circuitry comprising the steps of: providing a plurality of test cells having first and second memories. one or more of said test cells connected between the input to the integrated circuit and the application logic and one or more of said test cells connected between the output of said integrated circuit and said application logic; storing serial data in said first memory; transmitting serial data between the first memories of the test cells; and storing output data in said second memory.
Claim 28
Independent Claim
99 words
A method of observing and controlling information input to an output from an integrated circuit containing application logic circuitry comprising the steps of: providing a plurality of test cells having first and second memories. one or more of said test cells connected between the input to the integrated circuit and the application logic and one or more of said test cells connected between the output of said integrated circuit and said application logic; storing serial data in said first memory; transmitting serial data between the first memories of the test cells; and storing output data in said second memory.
Claim 29
Dependent Claim
29 words
The method of Claim 24 and further comprising the step of transferring data from said first memories of the respective cells to the second memories of said respective cells.
Claim 30
Dependent Claim
32 words
The method of Claim 24 and further comprising the step of transferring data stored in said second memories to the respective test cells to the first memories of said respective test cells.
Claim 31
Dependent Claim
27 words
The method of Claim 24 and further comprising the step of maintaining the output of said second memory at a given state responsive to a control signal.
Claim 32
Dependent Claim
24 words
The method of Claim 24 and further comprising the step of toggling the output of said second memory between first and second logic levels.
Claim 33
Dependent Claim
23 words
The method of Claim 24 and further comprising the step of loading said second memories of the test cells with predetermined logic values.
References Cited (Backward Citations)
No citation records indexed.
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