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EP0358330A1
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Programmable interrupt controller
Assignee: Compaq Computer Corp
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Filing: 1989-08-04
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Granted: —
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Expires: 2009-08-04
Abstract
Abstract A computer system includes a programmable interrupt controller (I) wherein individual interrupt levels can be programmed to receive edge or level sensed interrupt signals. The controller includes a programmable register (28) for storing the interrupt level designations for each interrupt level and associated interrupt recognition logic.
Inventors
- 👤 Paul R. Culley
- 👤 Montgomery Co. Mcgraw
- 👤 Karl N. Walker
- 👤 Lazaro D. Perez
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:37
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
202 words
A programmable interrupt controller (I) for a computer system including a processor and a plurality of peripheral devices connected to the processor for servicing in response to interrupt signals generated by the peripheral device, the programmable interrupt controller being connected between the processor and the peripheral devices, and comprising: means (20) for receiving and storing a plurality of interrupt request signals from the peripheral devices, the receiving means including a plurality of interrupt request input terminals (IR0-IR7). means (18,20) for assigning priorities to each of the interrupt request signals received; means (22) for resolving the highest priority among concurrent interrupt request signals, the priority resolving means including means for placing lower priority interrupt requests in a stand-by mode; means (18) for transmitting the selected interrupt request to said processor; means (16) for transmitting data concerning the peripheral device initiating the selected interrupt request to the processor; programmable means (20,28) for enabling the controller to recognize one of a plurality of interrupt request signal formats as valid, the programmable means including means (28) to allow the processor to read and write data designating the format of interrupt request signal to be considered valid for each of the interrupt request input terminals (IR0-IR7) individually.
Claim 2
Dependent Claim
202 words
A programmable interrupt controller (I) for a computer system including a processor and a plurality of peripheral devices connected to the processor for servicing in response to interrupt signals generated by the peripheral device, the programmable interrupt controller being connected between the processor and the peripheral devices, and comprising: means (20) for receiving and storing a plurality of interrupt request signals from the peripheral devices, the receiving means including a plurality of interrupt request input terminals (IR0-IR7). means (18,20) for assigning priorities to each of the interrupt request signals received; means (22) for resolving the highest priority among concurrent interrupt request signals, the priority resolving means including means for placing lower priority interrupt requests in a stand-by mode; means (18) for transmitting the selected interrupt request to said processor; means (16) for transmitting data concerning the peripheral device initiating the selected interrupt request to the processor; programmable means (20,28) for enabling the controller to recognize one of a plurality of interrupt request signal formats as valid, the programmable means including means (28) to allow the processor to read and write data designating the format of interrupt request signal to be considered valid for each of the interrupt request input terminals (IR0-IR7) individually.
Claim 3
Dependent Claim
81 words
An interrupt controller according to claim 1, wherein the programmable means comprises: register means (20,28) for storing data indicative of the format of interrupt request signal to be recognized as valid for each peripheral device; logic circuit means (30) for interfacing between the peripheral devices and the interrupt request receiving means (20), the logic means being arranged to provide an output signal having a common format upon the receipt of an interrupt request formatted in any one of the valid formats.
Claim 4
Dependent Claim
34 words
An interrupt controller according to claim 2, wherein the programmable means includes means for individually designating, for each interrupt request input terminal, edge sensed or level sensed formatted interrupt request signals as valid inputs.
Claim 5
Dependent Claim
21 words
An interrupt controller according to claim 3, wherein valid level sensed interrupt request signals comprise a level logic low voltage signal.
Claim 6
Dependent Claim
28 words
An interrupt controller according to claim 3, wherein valid edge sensed interrupt request signals comprise a signal changing from a logic low level to a logic high level.
Claim 7
Dependent Claim
206 words
An interrupt controller according to claim 3, wherein the logic circuit means (30) comprises: an interrupt request signal input line (IR0-IR7) for each peripheral device; a first logic circuit (32,36) connected to the interrupt input line; a second logic circuit (34,38) connected to the interrupt input line; the first logic circuit comprising: a first AND gate (36) having first and second input terminals and an output terminal, the first input terminal being connected to the interrupt request input terminal (42); a first inverter means (32) for inverting the data signal from the register means (28), connected between the register means and the second input of the first AND gate (36); the second logic circuit comprising: a second AND gate (38) having first and second input terminals and an output terminal, the first input terminal being connected to the register means (28); a second inverter means (34) for inverting the interrupt request signal, connected between the interrupt request input terminal (42) and the second input of the second AND gate (38); and an OR gate (40) having first and second input terminals and an output terminal; the first and second input terminals being connected to the output terminals of the first and second AND gates (36,38) respectively.
Claim 8
Dependent Claim
24 words
An interrupt controller further comprising: means (26) for selectively disabling the servicing of interrupt request signals from one or more of the peripheral devices.
Claim 9
Dependent Claim
24 words
An interrupt controller further comprising: means (26) for selectively disabling the servicing of interrupt request signals from one or more of the peripheral devices.
Claim 10
Dependent Claim
16 words
A computer system having a programmable interrupt controller according to any of claims 1 to 7.
Claim 11
Dependent Claim
80 words
A computer system according to claim 8, wherein the interrupt controller includes: means (10) for interconnecting the controller with one or more other controllers, the interconnecting means including means for designating one of the interconnected controllers as the master and the other controllers as a slave the master controller interfacing directly with the processor, and the slave controllers receiving interrupt requests which are prioritized, selected and passed to the master controller for further prioritization before being transmitted to the processor.
References Cited (Backward Citations)
US4631670A
Cited
DE8803950U1
Cited
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