Patent EP0358166A2 successfully refreshed from Google Patents.
EP0358166A2
Expired / Lapsed
EP
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Power saving arrangement and power saving method
Assignee: Sanyo Electric Co Ltd
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Filing: 1989-09-05
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Granted: —
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Expires: 2009-09-05
Abstract
Abstract A power saving arrangement for use in a handset unit which communicates with a base unit in response to the detection of an ID signal leading data signal, which are produced from the base unit, includes a processing circuit for receiving and processing the ID signal and data signal, and a detecting circuit, connected to the processing circuit, for detecting the ID signal and data signal. A CPU controls the power supply such that, under the first standby mode a reduced power is supplied to the processing circuit, and no power to the detecting circuit. Under the second standby mode as established when the detected level of the received signal exceeds a predetermined level, the reduced power is supplied to the processing circuit means and also to the detecting circuit means. Under the use mode as established when the detected ID signal has a predetermined pattern, full power is supplied to the processing circuit and also to the detecting circuit.
Inventors
- 👤 Kazuhisa Ishiguro
- 👤 Yutaka Sekiguchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 14:47
CPC Classifications
H; H04; H04W; H04W52/00; H04W52/02; H03; H03F; H03F1/00; H03F1/02; H03F1/0205; H03F1/0277; H04B; H04B1/00; H04B1/06; H04B1/16; H04W52/0209; H04W52/0225; H04W52/0229; H04W52/0261; H04W52/0274; H04W52/028; Y; Y02; Y02D; Y02D30/00; Y02D30/70
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
356 words
A power saving arrangement for use in a subsidiary unit which communicates with a base unit in response to the detection of an ID signal leading data signal which are produced from said base unit and received by said subsidiary unit, said power saving arrangement comprising: power control circuit for selectively producing a full power and a reduced power; a processing circuit means for receiving and processing said data signal when the full power is applied thereto, and for detecting the level of the received signal when the reduced electric power is applied thereto; detecting circuit means, connected to said processing circuit means, for detecting data signal when the full power is applied thereto, and for detecting only ID signal when the reduced power is applied thereto; first switching means for making and braking a power supply path to said detecting circuit means from said power control circuit; and control means for controlling said power control circuit and said first switching means to establish either one of first standby mode, second standby mode and use mode such that: under the first standby mode, said first switching means brakes the power supply to said detecting circuit means and, at the same time, power control circuit produces the reduced power to said processing circuit means, ready to detect the level of the received signal; under the second standby mode as established when said control means detects that the received signal level exceeds a predetermined level, said first switching means makes the power supply to said detecting circuit means and, at the same time, power control circuit produces the reduced power to said processing circuit means and also to said detecting circuit means, ready to detect and read the pattern of said ID signal; and under the use mode as established when said control means detects that said ID signal has a predetermined pattern, said first switching means makes the power supply to said detecting circuit means and, at the same time, power control circuit produces the full power to said processing circuit means and also to said detecting circuit means, ready to detect and read said data signal.
Claim 2
Dependent Claim
356 words
A power saving arrangement for use in a subsidiary unit which communicates with a base unit in response to the detection of an ID signal leading data signal which are produced from said base unit and received by said subsidiary unit, said power saving arrangement comprising: power control circuit for selectively producing a full power and a reduced power; a processing circuit means for receiving and processing said data signal when the full power is applied thereto, and for detecting the level of the received signal when the reduced electric power is applied thereto; detecting circuit means, connected to said processing circuit means, for detecting data signal when the full power is applied thereto, and for detecting only ID signal when the reduced power is applied thereto; first switching means for making and braking a power supply path to said detecting circuit means from said power control circuit; and control means for controlling said power control circuit and said first switching means to establish either one of first standby mode, second standby mode and use mode such that: under the first standby mode, said first switching means brakes the power supply to said detecting circuit means and, at the same time, power control circuit produces the reduced power to said processing circuit means, ready to detect the level of the received signal; under the second standby mode as established when said control means detects that the received signal level exceeds a predetermined level, said first switching means makes the power supply to said detecting circuit means and, at the same time, power control circuit produces the reduced power to said processing circuit means and also to said detecting circuit means, ready to detect and read the pattern of said ID signal; and under the use mode as established when said control means detects that said ID signal has a predetermined pattern, said first switching means makes the power supply to said detecting circuit means and, at the same time, power control circuit produces the full power to said processing circuit means and also to said detecting circuit means, ready to detect and read said data signal.
Claim 3
Dependent Claim
29 words
A power saving arrangement as claimed in Claim 1, wherein said processing circuit means comprises a signal strength detecting circuit for detecting the signal level of the received signal.
Claim 4
Dependent Claim
35 words
A power saving arrangement as claimed in Claim 2, further comprising a second switching means which operates synchronizingly with said first switching means for making and braking power supply to said signal strength detecting circuit.
Claim 5
Dependent Claim
19 words
A power saving arrangement as claimed in Claim 1, wherein said processing circuit means comprises a first stage amplifier.
Claim 6
Dependent Claim
23 words
A power saving arrangement as claimed in Claim 1, wherein said detecting circuit means comprises a second stage amplifier and a detector/modulator circuit.
Claim 7
Dependent Claim
16 words
A power saving arrangement as claimed in Claim 1, wherein said control means comprises a CPU.
Claim 8
Dependent Claim
27 words
A power saving arrangement as claimed in Claim 1, wherein said power control circuit comprises an operation control for producing said full power or said reduced power.
Claim 9
Dependent Claim
21 words
A power saving arrangement as claimed in Claim 7, wherein said operation control produces power intermittently thereby generating said reduced power.
Claim 10
Dependent Claim
197 words
A power saving method for use in a subsidiary unit which communicates with a base unit in response to the detection of an ID signal leading data signal which are produced from said base unit, said subsidiary unit having a processing circuit means for receiving and processing said ID signal and data signal, and a detecting circuit means, connected to said processing circuit means, for detecting said ID signal and data signal, the power saving method comprising the steps of: providing a reduced power to said processing circuit means and providing no power to said detecting circuit means, when ID signal and data signal are not present, ready to detect the level of the received signal by said processing circuit means; providing said reduced power to said processing circuit means and also to said detecting circuit means, when the detected received signal level exceeds a predetermined level, ready to detect the pattern of said ID signal by said detecting circuit means; and providing full power to said processing circuit means and also to said detecting circuit means, when the detected ID signal pattern is identical to a predetermined pattern, ready to detect and reproduce the data signal.
Claim 11
Dependent Claim
197 words
A power saving method for use in a subsidiary unit which communicates with a base unit in response to the detection of an ID signal leading data signal which are produced from said base unit, said subsidiary unit having a processing circuit means for receiving and processing said ID signal and data signal, and a detecting circuit means, connected to said processing circuit means, for detecting said ID signal and data signal, the power saving method comprising the steps of: providing a reduced power to said processing circuit means and providing no power to said detecting circuit means, when ID signal and data signal are not present, ready to detect the level of the received signal by said processing circuit means; providing said reduced power to said processing circuit means and also to said detecting circuit means, when the detected received signal level exceeds a predetermined level, ready to detect the pattern of said ID signal by said detecting circuit means; and providing full power to said processing circuit means and also to said detecting circuit means, when the detected ID signal pattern is identical to a predetermined pattern, ready to detect and reproduce the data signal.
Claim 12
Dependent Claim
20 words
A power saving method as claimed in Claim 9, wherein said reduced power is produced by intermittently generating the power.
References Cited (Backward Citations)
No citation records indexed.
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