Patent EP0357980A2 successfully refreshed from Google Patents.
EP0357980A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A memory cell with capacitance for single event upset protection
Assignee: Texas Instruments Inc
•
Filing: 1989-08-08
•
Granted: —
•
Expires: 2009-08-08
Abstract
Abstract A compact capacitor (24, 26) for use in a small memory cell in high density memories is disclosed. Such a capacitor (24, 26) in the cross-coupling of cross-coupled inverters (4, 5) in the memory cell improves single event upset hardness. The subject capacitor (24, 26) in its preferred embodiment is a MOS capacitor with both n+ and p+ connections to the capacitor channel so as to maintain a relatively high capacitance for both positive and negative capacitor gate voltages.
Inventors
- 👤 Terence G. W. Blake
- 👤 Theodore W. Houston
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 03:57
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/005; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125; H; H10; H10B; H10B10/00; H10B10/12; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
53 words
A memory cell including a pair of nodes of different voltages and further including a MOS capacitor connected across said nodes, said MOS capacitor including a gate region, a source/drain region and a channel region with both heavily doped n-type semiconductor material and heavily doped p-type semiconductor material connections to said channel region.
Claim 2
Dependent Claim
53 words
A memory cell including a pair of nodes of different voltages and further including a MOS capacitor connected across said nodes, said MOS capacitor including a gate region, a source/drain region and a channel region with both heavily doped n-type semiconductor material and heavily doped p-type semiconductor material connections to said channel region.
Claim 3
Dependent Claim
26 words
A memory cell as recited in claim 1 wherein said heavily doped n and p-type semiconductor materials of said MOS capacitor lie adjacent to one another.
Claim 4
Dependent Claim
23 words
A memory cell as recited in claim 2 wherein said adjacent heavily doped n and p-type semiconductor regions are connected together with silicide.
Claim 5
Dependent Claim
56 words
A memory cell including a pair of cross-coupled inverters and further including a MOS capacitor connected across the cross-couplings of said pair of inverters, said MOS capacitor including a gate region, a channel region and a source region comprising both heavily doped n-type semiconductor material and heavily doped p-type semiconductor material connected to said channel region.
Claim 6
Dependent Claim
56 words
A memory cell including a pair of cross-coupled inverters and further including a MOS capacitor connected across the cross-couplings of said pair of inverters, said MOS capacitor including a gate region, a channel region and a source region comprising both heavily doped n-type semiconductor material and heavily doped p-type semiconductor material connected to said channel region.
Claim 7
Dependent Claim
27 words
A memory cell as recited in claim 4 wherein said heavily doped n and p type semiconductor material of said MOS capacitor lie adjacent to one another.
Claim 8
Dependent Claim
24 words
A memory cell as recited in claim 4 wherein said adjacent heavily doped n and p type semiconductor material are connected together with silicide.
Claim 9
Dependent Claim
64 words
A memory cell as recited in claim 4 in which said gate region comprises a polycrystalline semiconductor region and said channel region comprises a lightly doped p-type semiconductor material and wherein said heavily doped n-type semiconductor material lies adjacent said heavily doped p-type semiconductor material and wherein said MOS capacitor further includes a gate oxide layer lying over said lightly doped p-type channel region.
Claim 10
Dependent Claim
17 words
A memory cell as recited in claim 7 wherein said adjacent semiconductor materials are connected by silicide.
Claim 11
Dependent Claim
64 words
A memory cell as recited in claim 4 in which said gate region comprises a polycrystalline semiconductor region and said channel region comprises a lightly doped n-type semiconductor material and wherein said heavily doped n-type semiconductor material lies adjacent said heavily doped p-type semiconductor material and wherein said MOS capacitor further includes a gate oxide layer lying over said lightly doped n-type channel region.
Claim 12
Dependent Claim
17 words
A memory cell as recited in claim 9 wherein said adjacent semiconductor materials are connected by silicide.
Claim 13
Dependent Claim
14 words
A memory cell as recited in claim 4 wherein said semiconductor material is silicon.
Claim 14
Dependent Claim
15 words
A memory cell as recited in claim 4 wherein said semiconductor material is gallium arsenide.
Claim 15
Dependent Claim
18 words
A memory cell as recited in claim 4 wherein said inverters include at least one field effect transistor.
Claim 16
Dependent Claim
40 words
A layout for the memory cell as recited in claim 13 wherein said MOS capacitor is formed by the extension of the gate of said at least one field effect transistor over the drain of said at least one transistor.
Claim 17
Dependent Claim
30 words
A layout for the memory cell as recited in claim 13 wherein said gate region of said MOS capacitor extends substantially along at least one dimension of said memory cell.
Claim 18
Dependent Claim
57 words
A memory cell including dynamic memory and including a pair of nodes of different voltages and further including a MOS capacitor connected across said nodes, said MOS capacitor including a gate region, a source region and a channel region with both heavily doped n-type semiconductor material and heavily doped p-type semiconductor material connections to said channel region.
Claim 19
Dependent Claim
57 words
A memory cell including dynamic memory and including a pair of nodes of different voltages and further including a MOS capacitor connected across said nodes, said MOS capacitor including a gate region, a source region and a channel region with both heavily doped n-type semiconductor material and heavily doped p-type semiconductor material connections to said channel region.
Claim 20
Dependent Claim
26 words
A memory cell as recited in claim 16 wherein said heavily doped n and p-type semiconductor material of said MOS capacitor lie adjacent to one another.
Claim 21
Dependent Claim
24 words
A memory cell as recited in claim 16 wherein said adjacent heavily doped n and p type semiconductor regions are connected together with silicide.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.