Patent EP0357503A2 successfully refreshed from Google Patents.
EP0357503A2
Expired / Lapsed
EP
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Programmable read only memory having bipolar complementary metal oxide semiconductor structure
Assignee: Fujitsu Ltd
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Filing: 1989-08-29
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Granted: —
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Expires: 2009-08-29
Abstract
Abstract A PROM having a BiCMOS structure comprises a memory cell array (2) having a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, an address transition detector (14) supplied with an address signal for detecting an address transition and for outputting a detection signal, a single variable load circuit (15) coupled to the address transition detector and having a load which is variably controlled responsive to the detection signal received from the address transition detector, a word line selection circuit (12) for selecting an arbitrary word line responsive to the address signal, and a bit line selection circuit (11) for selecting an arbitrary bit line responsive to the address signal and for supplying a current to only the selected arbitrary bit line, the current having a value dependent on the load of the variable load circuit.
Inventors
- 👤 Yasurou Matsuzaki
- 👤 Yuji Tsuchimoto
- 👤 Yoshikazu Mutoh
- 👤 Masaki Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 14:28
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
175 words
A programmable read only memory having a bipolar complementary metal oxide semiconductor structure, said programmable read only memory comprising a memory cell array (2) having a plurality of memory cells, each of the memory cells being connected to one of a plurality of bit lines (BL) and one of a plurality of word lines (WL), and a word line selection circuit (12) for selecting an arbitrary word line responsive to an address signal, characterized in that there are provided: an address transition detector (14) supplied with the address signal for detecting an address transition and for outputting a detection signal; a single variable load circuit (15) coupled to said address transition detector and having a load which is variably controlled responsive to the detection signal received from said address transition detector; and a bit line selection circuit (11) for selecting an arbitrary bit line responsive to the address signal and for supplying a current to only the selected arbitrary bit line, said current having a value dependent on the load of said variable load circuit.
Claim 2
Dependent Claim
175 words
A programmable read only memory having a bipolar complementary metal oxide semiconductor structure, said programmable read only memory comprising a memory cell array (2) having a plurality of memory cells, each of the memory cells being connected to one of a plurality of bit lines (BL) and one of a plurality of word lines (WL), and a word line selection circuit (12) for selecting an arbitrary word line responsive to an address signal, characterized in that there are provided: an address transition detector (14) supplied with the address signal for detecting an address transition and for outputting a detection signal; a single variable load circuit (15) coupled to said address transition detector and having a load which is variably controlled responsive to the detection signal received from said address transition detector; and a bit line selection circuit (11) for selecting an arbitrary bit line responsive to the address signal and for supplying a current to only the selected arbitrary bit line, said current having a value dependent on the load of said variable load circuit.
Claim 3
Dependent Claim
56 words
The programmable read only memory as claimed in claim 1, characterized in that there is further provided an output circuit means (16,17, 217) which is coupled to a node (B) which connects said variable load circuit (15) and said bit line selection circuit (11) for outputting a signal read out from said memory cell array (2).
Claim 4
Dependent Claim
59 words
The programmable read only memory as claimed in claim 2, characterized in that said output circuit means (16, 17, 217) comprises a sense amplifier (16) which receives a signal from said node (B), and an output circuit (17) which receives an output signal of said sense amplifier and outputs the signal read out from said memory cell array (2).
Claim 5
Dependent Claim
39 words
The programmable read only memory as claimed in any of claims 1 to 3, characterized in that the memory cells of said memory cell array (2) respectively have a junction which is destroyed and short-circuited when written with data.
Claim 6
Dependent Claim
77 words
The programmable read only memory as claimed in any of claims 1 to 4, characterized in that said variable load circuit (15) has a first load value when the address transition occurs and the detection signal is received from said address transition detector (14) and has a second load value when no address transition occurs and no detection signal is received from said address transition detector, said first load value being smaller than said second load value.
Claim 7
Dependent Claim
69 words
The programmable read only memory as claimed in claim 5, characterized in that said variable load circuit (15) comprises a transistor (Q2) and a resistor (R1) which are connected in parallel between a power source (Vcc) and a node (B), said transistor being controlled by the detection signal received from said address transition detector (14), said node connecting said variable load circuit and said bit line selection circuit (11).
Claim 8
Dependent Claim
55 words
The programmable read only memory as claimed in any of claims 1 to 6, characterized in that there is further provided a write current supplying circuit (13) for supplying a write current to an arbitrary bit line which is selected responsive to the address signal during a write mode of the programmable read only memory.
References Cited (Backward Citations)
No citation records indexed.
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