Sealed charge storage structure

Claim 2

A semiconductor charge storage structure comprising, a semiconductor substrate (17) and a first electrode (46) defined within the substrate, an electrically floating second electrode (15) disposed above the substrate (17) in electron injection communication relation relative to the first electrode (46), whereby the second electrode (15) stores accumulated electron charges, radiation shielding cover means (18), disposed over and around the floating second electrode (15) and contacting the substrate (19) in a ring surrounding the floating second electrode on all sides, completely enclosing the second electrode from the substrate upwardly in all directions totally to seal the second electrode from radiation, and conductive means defined within the substrate (17) to contact both the first electrode (46) and an electron charge source remote from the first electrode (46).

Claim 3

A sealed memory cell in a nonvolatile memory chip, the chip containing a plurality of memory cells formed in memory cell areas of the chip, at least one of the memory cells being sealed from exposure to radiant energy, the sealed memory cell comprising, a chip substrate (17), a source (11), a drain (13) and a floating gate (15) defined in a memory cell area of the chip substrate (17), a radiant energy shielding cover (18) in contact with the substrate (17) in a ring (19) completely enclosing the memory cell area, the memory cell area being totally sealed over and around all sides of the memory area from radiant energy by the cover (18), and means (31, 35, 45) defined within the chip substrate electrically to connect the source (11), the drain (13) and the floating gate (15) with corresponding connection terminals (39, 49) outside of the memory cell area, the floating gate (15) being capacitively coupled to its corresponding connection terminal (49).

Claim 4

A sealed memory cell in a nonvolatile memory chip, the chip containing a plurality of memory cells formed in memory cell areas of the chip, at least one of the memory cells being sealed from exposure to radiant energy, the sealed memory cell comprising, a chip substrate (17), a source (11), a drain (13) and a floating gate (15) defined in a memory cell area of the chip substrate (17), a radiant energy shielding cover (18) in contact with the substrate (17) in a ring (19) completely enclosing the memory cell area, the memory cell area being totally sealed over and around all sides of the memory area from radiant energy by the cover (18), and means (31, 35, 45) defined within the chip substrate electrically to connect the source (11), the drain (13) and the floating gate (15) with corresponding connection terminals (39, 49) outside of the memory cell area, the floating gate (15) being capacitively coupled to its corresponding connection terminal (49).

Claim 5

A sealed memory cell according to claim 2, wherein the connecting means comprises, a first electrically conductive channel (35) within the substrate extending from the drain (13) in the memory cell area, under the shielding cover (18), to a corresponding drain connection terminal (39), a second electrically conductive channel (45) within the substrate extending from a capacitive coupling area (46) located beneath an extension (41, 141) of the floating gate (15), under the shield cover (18), to a corresponding gate connection terminal (49), and a conductive line (31) electrically contacting the source (11) and the cover (18), the cover (18) being electrically conductive.

Claim 6

A sealed memory cell according to claim 3 wherein the first (35) and second (45) conductive channels comprise N-wells, buried N+ implant or buried N+ layers.

Claim 7

A sealed memory cell according to claim 3, wherein the floating gate extension (41) above the capacitive coupling area (46) has a polygonal shaped.

Claim 8

A sealed memory cell according to claim 3, wherein the floating gate extension (141) above the capacitive coupling area (46) has a forked shaped with a plurality of fingers.

Claim 9

A sealed memory cell according to claim 2, wherein the cover (18) is composed of metal, polysilicon or monocrystalline silicon.

Claim 10

A sealed memory cell in an EPROM device, the EPROM device having a substrate with a plurality of floating gate memory cells formed in memory cell areas of the substrate, at least one of the memory cells being sealed from erasure by ultraviolet light, the sealed memory cell comprising, spaced apart implants in a memory cell area of a substrate, the implants defining a source (11) and a drain (13), a thin gate oxide layer (21) disposed over the substrate between the source and drain implants, a polysilicon layer defining a floating gate (15), the polysilicon layer being disposed over the thin gate oxide layer (21) and extending therefrom to a coupling area (46), an ultraviolet-shielding electrically conductive cover (18) disposed on top of the substrate with top and sides thereof respectively spaced over and around the source (11), the drain (13) and the floating gate (15), the cover (18) contacting the substrate in a ring (23) completely surrounding the source (11), the drain (13) and the floating gate (15) whereby the memory cell is completely surrounded on top and sides by the cover (18), electrically conductive channels (35, 45) defined in the substrate extending under the sides of the cover (18), a first (35) of the channels extending from the drain implant (11) in the memory cell area to a drain connection implant (37) outside of the memory cell area, a second (45) of the channels extending from the coupling area (46) in the memory cell area to a gate connection implant (47) outside of the memory cell area, the coupling area (46) having an oxide layer (43) between the polysilicon layer and the second channel (45) whereby the second channel (45) is capacitively coupled to the floating gate (15), and means for electrically connecting the source implant to the conductive cover (18), conductive lines of the EPROM device electrically communicating with the source (11), the drain (13) and the gate (15) via the respective conductive cover, drain connection implant (37) and gate connection implant (47) outside the memory cell area.

Claim 11

A sealed memory cell in an EPROM device, the EPROM device having a substrate with a plurality of floating gate memory cells formed in memory cell areas of the substrate, at least one of the memory cells being sealed from erasure by ultraviolet light, the sealed memory cell comprising, spaced apart implants in a memory cell area of a substrate, the implants defining a source (11) and a drain (13), a thin gate oxide layer (21) disposed over the substrate between the source and drain implants, a polysilicon layer defining a floating gate (15), the polysilicon layer being disposed over the thin gate oxide layer (21) and extending therefrom to a coupling area (46), an ultraviolet-shielding electrically conductive cover (18) disposed on top of the substrate with top and sides thereof respectively spaced over and around the source (11), the drain (13) and the floating gate (15), the cover (18) contacting the substrate in a ring (23) completely surrounding the source (11), the drain (13) and the floating gate (15) whereby the memory cell is completely surrounded on top and sides by the cover (18), electrically conductive channels (35, 45) defined in the substrate extending under the sides of the cover (18), a first (35) of the channels extending from the drain implant (11) in the memory cell area to a drain connection implant (37) outside of the memory cell area, a second (45) of the channels extending from the coupling area (46) in the memory cell area to a gate connection implant (47) outside of the memory cell area, the coupling area (46) having an oxide layer (43) between the polysilicon layer and the second channel (45) whereby the second channel (45) is capacitively coupled to the floating gate (15), and means for electrically connecting the source implant to the conductive cover (18), conductive lines of the EPROM device electrically communicating with the source (11), the drain (13) and the gate (15) via the respective conductive cover, drain connection implant (37) and gate connection implant (47) outside the memory cell area.

Claim 12

A sealed memory cell according to claim 8, wherein the electrically conductive channels (35, 45) are N-wells, buried N+ implants or buried N+ layers.

Claim 13

A sealed memory cell according to claim 8, wherein the polysilicon layer (41) over the coupling area has a polygonal shape.

Claim 14

A sealed memory cell according to claim 8, wherein the polysilicon layer (141) over the coupling area has a forked shape with a plurality of fingers (143) disposed over the second channel (45).

Claim 15

A sealed memory cell according to claim 8, wherein the cover (18) is composed of metal, polysilicon or monocrystalline silicon.

Claim 16

A sealed memory cell according to claim 8, wherein the connecting means comprises a conductive layer (31) disposed over and contacting the source implant (11), the conductive layer (31) also contacting a side of the conductive cover (18).

Claim 17

A sealed memory cell according to claim 8, wherein the source (11) and drain (13) are defined by arsenic N+ implants.

Claim 18

A sealed memory cell according to claim 8, wherein a ring implant (23) is disposed in the substrate beneath the sides of the cover (18), the channels (35, 45) crossing under the ring implant (23) in crossing regions, the ring implant (23) being a P+ implant at least in the crossing regions.