Integrated Circuit Card

Claim 2

An IC card comprising: a processor (1); a first memory (11) for storing therein a system program which runs on said processor (1) and which is associated with a basic operation of said IC card; a second memory (9) for storing therein an application program which runs on said processor (1) and which corresponds to a usage of said IC card; a third memory (8) for storing therein data processed by said processor (1); an input/output unit (2) for effecting input and output operations of programs and data; program stop means (6) for stopping the program being executed on said processor (1) at a specified address; and data output means (4) for supplying said input/output unit (2) with either one of a content of a register in said processor (1) and a content of an area at an address of at least one of said first, second, and third memories (11, 9, 8) when the program running on said processor (1) is stopped.

Claim 3

An IC card according to Claim 1 further including means (11, 6) operative in response to mode identifying information included in a mode switch command inputted via said input/output unit (2) of said IC card in order to control an execution of the application program to be executed in an ordinary operation mode (31) for causing said program stop means (6) to operate to stop the program on said processor (1).

Claim 4

An IC card according to Claim 1 wherein said program stop means (6) includes a register (62) for keeping therein a stop address to be compared with an address signal received from an address bus connected to said processor (1).

Claim 5

An IC card according to Claim 1 wherein said program stop means (6) includes means for saving a content of an address for a stoppage in the application program and for keeping in place thereof a command code which can be executed by said processor (1).

Claim 6

An IC card comprising: a processor (3); a first nonvolatile memory section (11) for storing therein a basic processing program of said processor (3); a rewritable second nonvolatile memory section (9) for storing therein an application program associated with the basic processing program; a third memory section (8) comprising a rewritable nonvolatile or volatile memory for storing therein various kinds of processing data, thereby achieving data communications with an external device, said IC card further including: program initiate processing means (5) for causing said processor (3) to execute the application program beginning from an execution start address set to said second nonvolatile memory section (9); program stop means (6) operative during an execution of the application program for stopping the execution when a specified stop condition to stop the execution is satisfied; and data output means (4) for supplying the external device with a content of either one of an internal register of said processor (3), another register, and at least one selected from areas indicated by addresses specified in said second nonvolatile memory section (9) and in said third memory section (8), at least either one of the execution start address and the stop condition is set by use of the external device.

Claim 7

An IC card comprising: a processor (3); a first nonvolatile memory section (11) for storing therein a basic processing program of said processor (3); a rewritable second nonvolatile memory section (9) for storing therein an application program associated with the basic processing program; a third memory section (8) comprising a rewritable nonvolatile or volatile memory for storing therein various kinds of processing data, thereby achieving data communications with an external device, said IC card further including: program initiate processing means (5) for causing said processor (3) to execute the application program beginning from an execution start address set to said second nonvolatile memory section (9); program stop means (6) operative during an execution of the application program for stopping the execution when a specified stop condition to stop the execution is satisfied; and data output means (4) for supplying the external device with a content of either one of an internal register of said processor (3), another register, and at least one selected from areas indicated by addresses specified in said second nonvolatile memory section (9) and in said third memory section (8), at least either one of the execution start address and the stop condition is set by use of the external device.

Claim 8

An IC card according to Claim 5 having an ordinary operation mode (31) and a development mode (32), said ordinary operation mode (31) being disposed to enable said IC card to operate as an ordinary IC card and to enable the application program to be executed; said development mode (32) being disposed to enable an execution of the application program to be controlled through operations of said program initiate processing means (5), said program stop processing means (6), and said data output processing means (4), either one of said ordinary operation mode (31) and said development mode (32) being selected by the external device.

Claim 9

An IC card according to Claim 5 wherein said first nonvolatile memory section (11) comprises a mask ROM.

Claim 10

An IC card according to Claim 5 wherein said second nonvolatile memory section (9) and said third memory section (8) comprise an EEPROM.

Claim 11

An IC card according to Claim 8 wherein said second nonvolatile memory section (9) and said third memory section (8) are integrated in an EEPROM.

Claim 12

An IC card according to Claim 6 wherein said program initiate processing means (5) and said data output processing means (4) are included in said processor (3).

Claim 13

An IC card according to Claim 6 wherein said first nonvolatile memory section (11) contains a mode switch program effecting a change-over operation between said ordinary operation mode (31) and said development mode (32).

Claim 14

An IC card according to Claim 11 wherein said first nonvolatile memory section (11) comprises a mask ROM.

Claim 15

An IC card according to Claim 6 further including a debug data storage area to be loaded with debug data.