Large scale integrated EPROM device having a high coupling factor

Abstract

Abstract The present invention relates to an electrically programmable nonvolatile memory, composed of a grid of word lines (LM2) extending along rows, connecting control gates of floating-gate transistors (23), and of bit lines (LB1, LB2) extending along columns, connecting drains of the floating-gate transistors (23). A conductive zone (35), of dimensions greater than those of the floating gate (23) of the transistors along a horizontal plane, is connected to the floating gate (23) of each transistor of the memory, while being situated opposite the corresponding word line (LM2), from which it is separated by an insulating layer (28). <IMAGE>

Inventors

• 👤 Albert Bergemont

Bibliographic Details