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EP0352806A2
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Cache memory and access controller using such memory
Assignee: Toshiba Corp
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Filing: 1989-07-28
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Granted: —
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Expires: 2009-07-28
Abstract
Abstract A cache memory characterized by having, in the same chip, address tag divisions (13) storing address tags of stored data, a comparator (24) comparing an address tag (20) in external address (19) with the address tags in the address tag divisions (13), a circuit (25) generating internal hit signal depending on the output of the comparator (24) and an OR circuit (7) outputting an OR signal of the internal hit signal and an external signal.
Inventors
- 👤 Akio Miyoshi
- 👤 Yoshiki 304 Kamiooka Haidensu Hayakashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 05:40
CPC Classifications
G; G11; G11C; G11C7/00; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
79 words
A cache memory characterized by comprising, in the same chip, address tag divisions (13) storing address tags of stored data, a comparator (24) comparing an address tag (20) in external address (19) with the address tags in the address tag divisions (13), a circuit (25) generating an intertnal hit signal depending on the output of the collator (24), and an OR circuit (7) outputting an OR signal of logical sum of the internal hit signal and an external signal.
Claim 2
Dependent Claim
79 words
A cache memory characterized by comprising, in the same chip, address tag divisions (13) storing address tags of stored data, a comparator (24) comparing an address tag (20) in external address (19) with the address tags in the address tag divisions (13), a circuit (25) generating an intertnal hit signal depending on the output of the collator (24), and an OR circuit (7) outputting an OR signal of logical sum of the internal hit signal and an external signal.
Claim 3
Dependent Claim
27 words
A cache memory as defined in claim 1, characterized by having data divisions (11) storing the data and the address tag divisions (13) in the same chip.
Claim 4
Dependent Claim
35 words
A cache memory as defined in claim 1, characterized by having a latch circuit (28) latching the external hit signal and feeding the external hit signal to the OR circuit (7) in the same chip.
Claim 5
Dependent Claim
33 words
A cache memory as defined in claim 1, characterized by having a gate circuit (31) feeding the internal hit signal to the OR circuit (7) only when an external enable signal is given.
Claim 6
Dependent Claim
59 words
An access controller for a processor using a cache memory as defined in claim 1, characterized in that output of an I/O ready signal generation circuit (3) is given as the external signal to the cache memory (5) and the OR signal from the cache memory (5) is given to a ready signal input terminal of the processor (1).
Claim 7
Dependent Claim
80 words
An access controller for a processor utilizing a cache memory as defined in claim 4, characterized in that output of an I/O ready signal generation circuit (3) is given as the external hit signal to the cache memory (30), a chip enable signal from an address decoder (33) is given as the enable signal to the cache memory (30) and the OR signal from the cache memory (30) is given to a ready signal input terminal of the processor (1).
Claim 8
Dependent Claim
74 words
An access controller as defined in claim 5, characterized in that multiple cache memories (5₁, 5₂) are provided, the processor (34) has multiple ready signal input terminals (35₁, 35₂), the OR signals from said multiple cache memories (5₁, 5₂) are given to the ready signal input terminals (35₁, 35₂) respectively and the OR signal from each of the cache memory is given as the external hit signal to the other cache memories (5₁, 5₂).
Claim 9
Dependent Claim
74 words
An access controller as defined in claim 6, characterized in that multiple cache memories (5₁, 5₂) are provided, the processor (34) has multiple ready signal input terminals (35₁, 35₂), the OR signals from said multiple cache memories (5₁, 5₂) are given to the ready signal input terminals (35₁, 35₂) respectively and the OR signal from each of the cache memory is given as the external hit signal to the other cache memories (5₁, 5₂).
Claim 10
Dependent Claim
73 words
An access controller as defined in claim 5 or claim 6, characterized in that a main memory ready signal generation circuit (36) generating main memory ready signal when the internal hit signal has not been formed in the cache memory (5) is provided and outputs of the main memory ready signal generation circuit (36) and the I/O ready signal generation circuit (3) are given as the external signal to the cache memory (5).
Claim 11
Dependent Claim
70 words
An access controller as defined in claim 6, characterized in that a main memory ready signal generation circuit (36) generating main memory ready signal when the internal hit signal has not been formed in the cache memory (5) is provided and outputs of the main memory ready signal generation circuit (36) and the I/O ready signal generation circuit (3) are given as the external signal to the cache memory (5).
References Cited (Backward Citations)
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