Semiconductor memory

Claim 2

A semiconductor memory comprising: a semiconductor memory circuit (10), a counter section (2, 3) for causing at least a part of counters (3) to operate in association with an operation of said semiconductor memory circuit (10) and at least other part of counters (2) to operate by itself; and a counter comparator (4) for comparing the logic state of said two counters (2, 3) with each other, an output of said counter comparator (4) being used to control said semiconductor memory circuit (10).

Claim 3

A semiconductor memory comprising: a semiconductor memory circuit (10) including at least a dynamic memory cell, a counter section (2, 3) for causing at least a art of counters (3) to operate in association with an operation of said semiconductor memory circuit (10) and at least other part of counters (2) to operate by itself; and a counter comparator (4) for comparing the logic state of said two counters (2, 3) with each other, an output of said counter comparator (4) being used to control the refresh operation of said semiconductor memory circuit (10).

Claim 4

A semiconductor memory comprising: a semiconductor memory circuit (10) including at least a dynamic memory cell, a counter section (2, 3) for causing at least a art of counters (3) to operate in association with an operation of said semiconductor memory circuit (10) and at least other part of counters (2) to operate by itself; and a counter comparator (4) for comparing the logic state of said two counters (2, 3) with each other, an output of said counter comparator (4) being used to control the refresh operation of said semiconductor memory circuit (10).

Claim 5

The semiconductor memory according to claim 2, wherein said semiconductor memory circuit (10) comprises a refresh request controller (5) that is controlled by an output of said counter comparator (4), and that accepts an external request signal (φ1) for requesting operation of said semiconductor memory circuit (10), said part of counters (3) that is associated with the refresh operation increases by refreshing operations actually executed for said semiconductor memory circuit (10), said part of counters (3) that is associated with the refresh operation increases by refreshing operations actually executed for said semiconductor memory circuit (10), said part of counters (2) that operate by itself increases by refreshing operations required of said semiconductor memory circuit (10).

Claim 6

The semiconductor memory according to claim 3, further comprising a refresh request controller (5) that is controlled to be in a disabled state by an output of said counter comparator (4) produced when detecting a coincidence and to be in an enabled state by an output of said counter comparator (4) produced when detecting a non-coincidence, said refresh request controller (5) in said enabled state accepting said external refresh request signal (φ1) and outputting an internal refresh request signal (φ2).

Claim 7

A semiconductor memory comprising: a semiconductor memory circuit (10), a counters section (2, 3) for causing at least a part of counters (3) to operate in association with an operation of said semiconductor memory circuit (10) and at least other part of counters (2) to operate by itself; a counter comparator (4) for comparing the logic state of said two counters (2, 3) with each other, an output of said counter comparator (4) being used to control said semiconductor memory circuit (10); and a latch circuit (41), coupled on an output of said comparator (4), and being subjected to latch control by at least one (φ4) of clock pulses (φ4, φ3) supplied to said two counters (2, 3) to be in a latch state to retain a previous state by closing an input thereof until an output level of said comparator (4) becomes stable after a change occurs in a content of that counter (2) which is supplied with said at least one clock pulse (φ4), said latch state being released after said output level of said comparator (4) becomes stable, a latch output of said latch circuit (41) being used to control said semiconductor memory circuit (10).

Claim 8

A semiconductor memory comprising: a semiconductor memory circuit (10), a counters section (2, 3) for causing at least a part of counters (3) to operate in association with an operation of said semiconductor memory circuit (10) and at least other part of counters (2) to operate by itself; a counter comparator (4) for comparing the logic state of said two counters (2, 3) with each other, an output of said counter comparator (4) being used to control said semiconductor memory circuit (10); and a latch circuit (41), coupled on an output of said comparator (4), and being subjected to latch control by at least one (φ4) of clock pulses (φ4, φ3) supplied to said two counters (2, 3) to be in a latch state to retain a previous state by closing an input thereof until an output level of said comparator (4) becomes stable after a change occurs in a content of that counter (2) which is supplied with said at least one clock pulse (φ4), said latch state being released after said output level of said comparator (4) becomes stable, a latch output of said latch circuit (41) being used to control said semiconductor memory circuit (10).

Claim 9

A semiconductor memory comprising: a semiconductor memory circuit (10) including at least a dynamic memory cell, a counter section (2, 3) for causing at least a part of counters (3) to operate in association with an operation of said semiconductor memory circuit (10) and at least other part of counters (2) to operate by itself; a counter comparator (2) for comparing the logic state of said two counters (2, 3) with each other, an output of said counter comparator (4) being used to control the refresh operation of said semiconductor memory circuit (10); and a latch circuit (41), coupled on an output of said comparator (4), and being subjected to latch control by at least one of clock pulses (φ4) supplied to said two counters (2, 3) to be in a latch state to retain a previous state by closing an input thereof until an output level of said comparator (4) becomes stable after a change occurs in a content of that counter (2) which is supplied with said at least one clock pulse (φ4), said latch state being released after said output level of said comparator (4) becomes stable, a latch output of said latch circuit (41) being used to control said semiconductor memory circuit (10).

Claim 10

A semiconductor memory comprising: a semiconductor memory circuit (10) including at least a dynamic memory cell, a counter section (2, 3) for causing at least a part of counters (3) to operate in association with an operation of said semiconductor memory circuit (10) and at least other part of counters (2) to operate by itself; a counter comparator (2) for comparing the logic state of said two counters (2, 3) with each other, an output of said counter comparator (4) being used to control the refresh operation of said semiconductor memory circuit (10); and a latch circuit (41), coupled on an output of said comparator (4), and being subjected to latch control by at least one of clock pulses (φ4) supplied to said two counters (2, 3) to be in a latch state to retain a previous state by closing an input thereof until an output level of said comparator (4) becomes stable after a change occurs in a content of that counter (2) which is supplied with said at least one clock pulse (φ4), said latch state being released after said output level of said comparator (4) becomes stable, a latch output of said latch circuit (41) being used to control said semiconductor memory circuit (10).

Claim 11

The semiconductor memory according to claim 6, wherein said semiconductor memory circuit (10) comprises a refresh request controller (5) that is controlled by an output of said counter comparator (4), and that accepts an external refresh request signal (φ1) for requesting operation of said semiconductor memory circuit (10), said part of counters (3) that is associated with the refresh operation increases by refreshing operations actually executed for said semiconductor memory circuit (10), said part of counters (2) that operate by itself increases by refreshing operations required of said semiconductor memory circuit (10).

Claim 12

The semiconductor memory according to claim 7, further comprising a refresh request controller (5) that is controlled to be in a disabled state by an output of said counter comparator (4) produced when detecting a coincidence and to be in an enabled state by an output of said counter comparator (4) produced when detecting a non-coincidence, said refresh request controller (5) in said enabled state accepting said external refresh request signal (φ1) and outputting an internal refresh request signal (φ2).