EP0352633A2 — A pipeline having an integral cache for computer …

Claim 1

Independent Claim 149 words

A load/store pipeline in a vector processor for loading data entries to registers and storing data entries from said registers, the pipeline comprising: a cache memory for storing data entries; a data loading device which loads data entries from said cache memory to said registers and which stores data from said registers in said cache memory with loading and storing data entries to said cache memory being pipelined; a determining device which determines when one of said entries is a miss; read miss buffers coupled to said miss determining device which store command addresses associated with said missed data entries and obtaining data entries from out of said pipeline independently of the operation of said pipeline, said data entries corresponding to said command addresses; and a filling device which fills the cache memory with said command address data entries and writes said command address data entries to said registers.

Claim 2

Dependent Claim 149 words

A load/store pipeline in a vector processor for loading data entries to registers and storing data entries from said registers, the pipeline comprising: a cache memory for storing data entries; a data loading device which loads data entries from said cache memory to said registers and which stores data from said registers in said cache memory with loading and storing data entries to said cache memory being pipelined; a determining device which determines when one of said entries is a miss; read miss buffers coupled to said miss determining device which store command addresses associated with said missed data entries and obtaining data entries from out of said pipeline independently of the operation of said pipeline, said data entries corresponding to said command addresses; and a filling device which fills the cache memory with said command address data entries and writes said command address data entries to said registers.

Claim 3

Dependent Claim 54 words

The load/store pipeline of claim 1, wherein said read miss buffers include buffers which store said command addresses, receive said command address data entries in arbitrary order from out of said pipeline and fill the cache memory with the data entries in the order the command addresses were stored in said read miss buffers.

Claim 4

Dependent Claim 118 words

The load/store pipeline of claim 1, wherein said determining device includes: a cache tag look up stage for parsing a physical address into a cache index and tag compare data; a tag store coupled to the cache tag look up stage for storing tags associated with addresses in said cache, said tag store receiving said cache index and outputting corresponding tag data; and a comparator coupled to said tag store and said cache tag look up stage for receiving said tag data and said rag compare data and generating a hit signal when said tag data and said tag compare data match, and a miss signal when said tag data and said tag compare data do not match.

Claim 5

Dependent Claim 34 words

The load/store pipeline of claim 3, further comprising a delay coupled between said cache tag look up stage and said cache memory for delaying receipt of said cache tag address by said cache memory.

Claim 6

Dependent Claim 33 words

The load/store pipeline of claim 4, further comprising an address generator coupled to said cache tag look up stage for receiving load and store commands and generating pipe entries which include virtual addresses.

Claim 7

Dependent Claim 30 words

The load/store pipeline of claim 5, further comprising a translation buffer coupled between said cache tag lookup stage and said address generator for translating said virtual addresses into physical addresses.

Claim 8

Dependent Claim 52 words

The load/store pipeline of claim 1, wherein said read miss buffers include buffers for store said command addresses, receiving said command address data in arbitrary order from out of said pipeline and fill the cache memory with the data in the order the command addresses were stored in said read miss buffers.

Claim 9

Dependent Claim 25 words

The load/store pipeline of claim 7, wherein said cache memory is coupled to said cache look up stage so as to receive said cache index.

Claim 10

Dependent Claim 28 words

The load/store pipeline of claim 1, further comprising a load/store controller for controlling the pipeline into either a load mode, a store mode or a cache fill mode.

Claim 11

Dependent Claim 60 words

The load/store pipeline of claim 1, wherein said loading device includes a cache data bus coupled to said cache memory and to said registers which transfers data entries between said cache memory and said registers; and said filling device includes an internal data bus coupling said read miss buffers to said cache data bus and carrying said command address data.

Claim 12

Dependent Claim 55 words

The load/store pipeline of claim 1, wherein said read miss buffers include obtaining devices which obtain additional data entries from out of said pipeline when said data entry corresponding to said command address is obtained, and wherein said filling device fills the cache memory with said command address data entry and said additional data entries.

Claim 13

Dependent Claim 33 words

The load/store pipeline of claim 11, wherein said data entries are longwords, and said additional data entries are longwords within an aligned hexaword which contains a longword corresponding to said command address data.

Claim 14

Dependent Claim 15 words

The load/store pipeline of claim 1, wherein said data is a quadword having two longwords.

Claim 15

Dependent Claim 28 words

The load/store pipeline of claim 13, wherein said entries contain information regarding alignment of said longwords within a quadword such that nonaligned longwords are storable in said registers.

Claim 16

Dependent Claim 33 words

The load/store pipeline of claim 14, wherein said information is cycle type information and said register is presented by said pipeline with an address and an address plus 1 for each said quadword.

Claim 17

Dependent Claim 72 words

The load/store pipeline of claim 1, further comprising a write buffer coupled to said cache memory which buffers data entries corresponding to a storing operation out of said pipeline, said write buffer having a capacity to store contents of an entire register, such that an operation subsequent to said storing operation can be performed in said pipeline while said data entries corresponding to said storing operation are buffered out of said pipeline.

Claim 18

Dependent Claim 27 words

The load/store pipeline of claim 16, wherein said write buffer is a dynamically configurable write buffer which is configurable during storing operations to accommodate different data formats.

Claim 19

Independent Claim 150 words

A method of loading data from a cache to registers in a vector processor, the method comprising the steps of: a) requesting a data block from said cache; b) checking whether there is a hit in said cache for said block of data to be loaded, said hit indicating that said data block is in said cache, and a miss indicating said data block is not in said cache; c) driving said data block from said cache to said registers when there is a hit; and d) obtaining said data block from a memory when there is a miss and writing said obtained data block into said cache and said registers, wherein steps a, b and c are repeated for subsequent data elements, and wherein the step of the obtaining of said data element is performed during the repeating of steps a, b and c for said subsequent data elements.

Claim 20

Independent Claim 150 words

A method of loading data from a cache to registers in a vector processor, the method comprising the steps of: a) requesting a data block from said cache; b) checking whether there is a hit in said cache for said block of data to be loaded, said hit indicating that said data block is in said cache, and a miss indicating said data block is not in said cache; c) driving said data block from said cache to said registers when there is a hit; and d) obtaining said data block from a memory when there is a miss and writing said obtained data block into said cache and said registers, wherein steps a, b and c are repeated for subsequent data elements, and wherein the step of the obtaining of said data element is performed during the repeating of steps a, b and c for said subsequent data elements.

Claim 21

Dependent Claim 55 words

The method of claim 18, wherein step d) includes the steps of sending a command address to at least one read miss buffer, receiving in said read miss buffer said data block from the memory over an external bus, and sending said data block to said cache and said registers via an internal data bus.

Claim 22

Dependent Claim 40 words

The method of claim 19, wherein said data block includes a plurality of individual data elements, and said read miss buffer sends said data block only when all said data elements of said data block are received from the memory.

Claim 23

Dependent Claim 97 words

The method of claim 20, wherein a plurality of read miss buffers are provided, and further comprising the steps of: e) halting the repeating of steps a, b and c when all of said read miss buffers contain a command address; f) writing an obtained data block in one of said read miss buffers into said cache and said registers; and g) repeating steps a, b, c and d until all said read miss buffers contain command addresses and then repeating steps e, f and g, until all of said data blocks are loaded into said registers.

Claim 24

Dependent Claim 66 words

The method of claim 19, wherein step d includes obtaining said data block and further data blocks when there is a miss, and said read miss buffer sends said data block and said further data blocks to said cache and said registers, with said data block and said further data blocks being filled in said cache and only said data block being written into said registers.

Claim 25

Dependent Claim 29 words

The method of claim 18, wherein said loading of data occurs simultaneously with a portion of a previous storing operation in which data blocks are sent to said memory.

Claim 26

Dependent Claim 23 words

The method of claim 23, further comprising the step of halting said storing operation when there is a miss during the loading operation.

Claim 27

Dependent Claim 131 words

A pipeline in a computer processor for loading data entries to registers and storing data entries from said registers, the pipeline comprising: a cache memory for storing data; a loading device which loads data entries from said cache memory to said registers and which stores data entries from said registers in said cache memory with loading and storing data entries to said cache memory being pipelined; a determining device which determines when one of said data entries is a miss and which obtains return data entries from out of said pipeline independently of the operation of said pipeline when one of said data entries is a miss, said returned data entry corresponding to said missed data entry; and a filling device which fills the cache memory with said returned data entry.

Claim 28

Dependent Claim 131 words

A pipeline in a computer processor for loading data entries to registers and storing data entries from said registers, the pipeline comprising: a cache memory for storing data; a loading device which loads data entries from said cache memory to said registers and which stores data entries from said registers in said cache memory with loading and storing data entries to said cache memory being pipelined; a determining device which determines when one of said data entries is a miss and which obtains return data entries from out of said pipeline independently of the operation of said pipeline when one of said data entries is a miss, said returned data entry corresponding to said missed data entry; and a filling device which fills the cache memory with said returned data entry.

Claim 29

Dependent Claim 46 words

The pipeline of claim 25, further including a controller which aborts instructions within said pipeline when one of said missed data entries corresponds to a load instruction and one of said data entries within said pipeline corresponds to a store instruction subsequent to said load instruction.

Claim 30

Dependent Claim 52 words

The pipeline of claim 26, further including a content addressable memory which compares information in said missed data entries which correspond to said load instructions with information in said data entries which correspond to said store instruction and causes said controller to abort said instructions within said pipeline based on said comparison.

Claim 31

Dependent Claim 231 words

A load/store pipeline in a scaler processor for loading data to registers and storing data from said registers, the pipeline comprising a register file which holds the results of an arithmetic logic operation; a translation buffer and a cache tag look up which are both coupled in parallel to the register file and receive a virtual address from the register file, said translation buffer performing a translation of the virtual address into a physical address, the cache tag look up performing a look up on untranslated bits of said virtual address; a comparator for comparing an output of said cache tag look up and an output of said translation buffer and producing a hit or miss signal based on said comparison; a data cache coupled to said translation buffer which stores data when there is a hit signal generated by said comparator; an output fifo coupled to said translation buffer which sends information out of said pipeline when there is a miss signal generated by said comparator to request data which is to be filled into said data cache; an input buffer coupled to said data cache which receives data from out of said pipeline which is to be filled into said data cache; and a memory reference tag which sends the tag corresponding to the data received by the input fifo to be stored in said cache tag look up.

Claim 32

Dependent Claim 231 words

A load/store pipeline in a scaler processor for loading data to registers and storing data from said registers, the pipeline comprising a register file which holds the results of an arithmetic logic operation; a translation buffer and a cache tag look up which are both coupled in parallel to the register file and receive a virtual address from the register file, said translation buffer performing a translation of the virtual address into a physical address, the cache tag look up performing a look up on untranslated bits of said virtual address; a comparator for comparing an output of said cache tag look up and an output of said translation buffer and producing a hit or miss signal based on said comparison; a data cache coupled to said translation buffer which stores data when there is a hit signal generated by said comparator; an output fifo coupled to said translation buffer which sends information out of said pipeline when there is a miss signal generated by said comparator to request data which is to be filled into said data cache; an input buffer coupled to said data cache which receives data from out of said pipeline which is to be filled into said data cache; and a memory reference tag which sends the tag corresponding to the data received by the input fifo to be stored in said cache tag look up.

Claim 33

Dependent Claim 239 words

A pipeline in a computer processor for loading data from a cache memory to registers and storing data from the registers to the cache memory, which pipeline comprises: an address generator operating to generate address information entries serially, each one of the address information entries relating to a corresponding one of a series of data entries; a cache tag lookup and comparator device coupled to the address generator to receive the address information entries serially from the address generator and operating to perform a cache tag lookup and tag compare operation, serially, for each one of the address information entries; and a data cache including a coupling to each of the address generator and the registers to receive the address information entries, serially, from the address generator and operating to selectively perform in respect of each of the data entries corresponding to the address information entries, one of a load of the each of the data entries from the cache memory to the registers and a store of each one of the data entries from the registers to the cache memory; the coupling between the data cache and the address generator including a delay device operating to delay the receiving of each one of the address information entries by the data cache relative to the receiving of the each one of the address information entries by the cache tag lookup and comparator device by at least one cycle time.

Claim 34

Dependent Claim 239 words

A pipeline in a computer processor for loading data from a cache memory to registers and storing data from the registers to the cache memory, which pipeline comprises: an address generator operating to generate address information entries serially, each one of the address information entries relating to a corresponding one of a series of data entries; a cache tag lookup and comparator device coupled to the address generator to receive the address information entries serially from the address generator and operating to perform a cache tag lookup and tag compare operation, serially, for each one of the address information entries; and a data cache including a coupling to each of the address generator and the registers to receive the address information entries, serially, from the address generator and operating to selectively perform in respect of each of the data entries corresponding to the address information entries, one of a load of the each of the data entries from the cache memory to the registers and a store of each one of the data entries from the registers to the cache memory; the coupling between the data cache and the address generator including a delay device operating to delay the receiving of each one of the address information entries by the data cache relative to the receiving of the each one of the address information entries by the cache tag lookup and comparator device by at least one cycle time.

A pipeline having an integral cache for computer processors

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