Semiconductor memory device with flash write mode of operation

Claim 1

A semiconductor memory device having a read-out mode of operation, a single bit write mode of operation and a flash write mode of operation, comprising: a) a memory cell array having a plurality of memory cells arranged in rows and columns; b) a plurality of word lines coupled to the memory cells of the rows, respectively; c) a plurality of bit line pairs respectively coupled to the memory cells of the columns, respectively, and operative to propagate data bits in the form of differences in voltage level, respectively, said bit line pairs having first bit lines respec­tively paired with second bit lines; d) a row addressing facility supplied with row address bits and operative to activate one of the word lines for providing data paths between the bit line pairs and the memory cells cou­pled thereto; e) sense amplifier circuits respectively coupled to the bit line pairs and responsive to activation signals for increasing the differences in voltage level; f) an input-and-output data facility supplied with a single bit write data bit in the single bit write mode of operation and with a flash write data bit in the flash write mode of operation; g) an input-and-output data bus system coupled to said input-and-output data facility for propagating the single bit write data bit in the form of a difference in voltage level in the single bit write mode of operation; h) a column addressing facility supplied with column address bits and operative to produce a multi-bit output signal in the single bit write mode of operation; and i) a column switch circuit having a plurality of switching units respectively coupled between said bit line pairs and the input-and-output data bus system, and responsive to said multi-­bit output signal to provide a data path between one of the bit line pairs and the input-and-output data bus system, character­ized in that said semiconductor memory device further comprises j) a flash write data bus system coupled to said input-and-­output data facility for propagating the flash write data bit in the form of either high or low voltage level in the flash write mode of operation; k) a controlling unit supplied with external control signals including a flash write enable signal, and operative to produce internal control signals including said activation signals in every mode of operation and a flash write switch controlling signal in the flash write mode of operation; and l) a flash write switch circuit having a plurality of switch­ing units respectively coupled between the flash write data bus system and either of said first bit lines and said second bit lines, and responsive to the flash write switch controlling signal to simultaneously provide data paths therebetween.