Output circuit

Abstract

Abstract An output circuit of this invention includes a first MOS transistor (8) inserted between a first poten­tial (V CC ) and an output terminal (Out), a level shift transistor (1) inserted between the first potential (V CC ) and the gate of the first MOS transistor (8), a second MOS transistor (3), a drain-source path of which is inserted between a control terminal of the level shift transistor (1) and a second potential (V SS ), and the gate of which receives a first control signal, a constant voltage element (10) inserted between the gate of the first MOS transistor (3) and the output terminal (Out), a third MOS transistor (7), a drain-source path of which is inserted between the output terminal (Out) and the second potential (V SS ) through the constant voltage element (10), and the gate of which receives a second control signal having a phase opposite to that of the first control signal, a signal delay circuit (12) for delaying the second control signal by a predeter­mined period of time to output a third control signal, and a fourth MOS transistor (11), a drain-source path of which is inserted between the output terminal (Out) and the second potential (V SS ), and the gate of which receives the third control signal, wherein the element size of the third MOS transistor (7) is set to be smaller than that of the fourth MOS transistor (11).

Inventors

• 👤 Masaji Ueno

Bibliographic Details