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EP0351820A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Output circuit

Assignee: Toshiba Corp
•
Filing: 1989-07-19
•
Granted: —
•
Expires: 2009-07-19
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Abstract

Abstract An output circuit of this invention includes a first MOS transistor (8) inserted between a first poten­tial (V CC ) and an output terminal (Out), a level shift transistor (1) inserted between the first potential (V CC ) and the gate of the first MOS transistor (8), a second MOS transistor (3), a drain-source path of which is inserted between a control terminal of the level shift transistor (1) and a second potential (V SS ), and the gate of which receives a first control signal, a constant voltage element (10) inserted between the gate of the first MOS transistor (3) and the output terminal (Out), a third MOS transistor (7), a drain-source path of which is inserted between the output terminal (Out) and the second potential (V SS ) through the constant voltage element (10), and the gate of which receives a second control signal having a phase opposite to that of the first control signal, a signal delay circuit (12) for delaying the second control signal by a predeter­mined period of time to output a third control signal, and a fourth MOS transistor (11), a drain-source path of which is inserted between the output terminal (Out) and the second potential (V SS ), and the gate of which receives the third control signal, wherein the element size of the third MOS transistor (7) is set to be smaller than that of the fourth MOS transistor (11).

Inventors

  • 👤 Masaji Ueno

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-26 13:34
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/0008; H03K19/0013; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K5/13; H03K5/133; H03K5/134

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 246 words
An output circuit comprising: a first MOS transistor (8), a source-drain path of which is connected between a first potential (V DD ) and an output terminal (Out); a level shift bipolar transistor (1) having a multicollector structure connected between said first potential (V CC ) and a gate of said first MOS transistor (8); a second MOS transistor (3), a source-drain path of which is connected between a control terminal of said bipolar transistor (1) and a second potential (V SS ), and a gate of which receives a first control signal; a constant voltage element (10) connected between a gate of said first MOS transistor (8) and said output terminal (Out); a third MOS transistor (7) having an element size smaller than that of a fourth MOS transistor (11), a source-drain path of said third MOS transistor being connected between a node of said gate of said first MOS transistor (8), a first collector of said bipolar tran­sistor (1), and said constant voltage element (10), and said second potential (V SS ), and a gate of said third MOS transistor receiving a second control signal having a phase opposite to that of the first control signal; and the fourth MOS transistor (11), a source-drain path of which is connected between said output terminal (Out) and said second potential (V SS ), and a gate of which receives a third control signal obtained by delaying the second control signal by a predetermined period of time.
Claim 2
Dependent Claim 246 words
An output circuit comprising: a first MOS transistor (8), a source-drain path of which is connected between a first potential (V DD ) and an output terminal (Out); a level shift bipolar transistor (1) having a multicollector structure connected between said first potential (V CC ) and a gate of said first MOS transistor (8); a second MOS transistor (3), a source-drain path of which is connected between a control terminal of said bipolar transistor (1) and a second potential (V SS ), and a gate of which receives a first control signal; a constant voltage element (10) connected between a gate of said first MOS transistor (8) and said output terminal (Out); a third MOS transistor (7) having an element size smaller than that of a fourth MOS transistor (11), a source-drain path of said third MOS transistor being connected between a node of said gate of said first MOS transistor (8), a first collector of said bipolar tran­sistor (1), and said constant voltage element (10), and said second potential (V SS ), and a gate of said third MOS transistor receiving a second control signal having a phase opposite to that of the first control signal; and the fourth MOS transistor (11), a source-drain path of which is connected between said output terminal (Out) and said second potential (V SS ), and a gate of which receives a third control signal obtained by delaying the second control signal by a predetermined period of time.
Claim 3
Dependent Claim 25 words
A circuit according to claim 1, characterized in that the second control signal is obtained by invert­ing the first control signal by an inverter (5).
Claim 4
Dependent Claim 72 words
A circuit according to claim 1, characterized in that the third control signal is obtained by a signal delay controller (12) comprising an AND gate (14), one input terminal of which receives the second control signal, and the other input terminal of which receives the second control signal delayed by a predetermined period of time, and a delay circuit (13) for delaying the second control signal by the predetermined period of time.

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